Kabushiki Kaisha Toshiba

Tsutomu Minagawa

Naoyuki Kai

Masahide Ohhashi

Yukimasa Uchida

A DMA controller having an acceptance circuit, a transfer control circuit and a release ordering circuit. The acceptance circuit receives a temporary bus release request and its withdrawal from an external device, once the DMA controller acquires a bus utility right from a CPU. The transfer control circuit then interrupts bus transfer cycles under operation and holds the bus transfer parameters so as to allow a restarting of the bus transfer cycle after the withdrawal is accepted. The release ordering circuit informs the external device of the permission of temporary bus use. So, buses are temporarily released against the external device by the DMA controller of the present invention without passing through the CPU.

DMA controller which releases buses to external devices without

A painting pattern generation system for painting interior areas enclosed by outlines indicated by outline data and flag data. This includes a first memory for storing outline data, a second memory for storing flag data, and an operational circuit for reading out the outline data. The flag data in the first and the second memories performs a logical exclusive OR operation on adjacent items of the flag data in the second memory in a scan line direction, and performs an OR operation between the result of the logical exclusive OR operation and the outline data in the first memory in all of the scan line directions. Thus obtaining the painted pattern data, and a writing circuit for writing the painted pattern data obtained by the operational circuit to overlap it with subsequent outline data in the first memory.

Painting pattern generation system using outline data and flag data

A pattern data generating system has a processor for writing in a bit map memory, on the basis of input data, points of all lines to be filled or painted along a scan direction which is one direction on the bit map memory. This writing is performed such that a point on each line is written as one of the two end points of the line thereof while a point, offset by one point in the scan direction, is written as the other of the two end points of the line. The pattern data generating system also has a pattern data generating circuit for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on one scan line, writing EXOR of data of points b0, b1, . . . , b(j-1) at positions corresponding to points b(j) (j is not less than 0 and less than w). Similar EXOR data writing is performed by the pattern data generating circuit for all the scan lines. Then, pattern data, in which the area surrounded by the closed curve is filled or painted, is obtained.

Pattern data generating system

A bit mask generator comprises partial mask generators for generating partial mask data corresponding to a plurality of blocks obtained by dividing input data, and parity correction circuits for correcting the partial mask data in accordance with a parity input and generating parity outputs. Each of the partial mask generators includes a plurality of first exclusive OR gates each of which receives bit data of a corresponding block as one input and input data of an LSB (Least Significant Bit) or an output of a lower-bit first exclusive OR gate as the other input. Each of the parity correction circuits includes a plurality of second exclusive OR gates each of which receives as one input the partial mask data generated by the partial mask generator of a corresponding block and as the other input a parity generated by a lower-bit parity correction circuit. An output from each second exclusive OR gate is generated as mask data of the corresponding block, and an output from the MSB (Most Significant Bit) second exclusive OR gate is generated as the parity.

Bit mask generator

A pattern data generating system comprises first and second bit map memories, a first control block for sequentially generating points corresponding to the boundaries of a closed curve in response to changes dx and dy along x and y directions, and writing the points in the first bit map memory, a second control block for sequentially generating points, which are required to paint an area enclosed by the closed curve, on the basis of the changes dx and dy, in accordance with a predetermined rule, and writing the points in the second bit map memory, a third control block for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on a single scan line provided that one direction is set to be a scan direction on the second bit map memory, sequentially writing EXOR data of the points b0, b1, . . . , b(j-1) (j is not less than 0 and less than w) at positions corresponding to points b(j), and a fourth control block for obtaining pattern data by final filling or painting in which an arithmetic operation (e.g., logical OR or logical AND) of data of an arbitrary point in the first bit map memory with data of a corresponding point in the second bit map memory which stores the EXOR data is performed.

A memory device having an operating function includes a memory cell array, a register, and a logical opeation circuit. The memory cell array has memory cells arranged in a matrix form of m rows .times.n columns. Data readout or write-in operation with respect to the memory cell array is effected in the unit of n bits of one row. The register has a bit width corresponding to one row of the memory cell array. Data of one row is read out from the memory cell array and is processed by the logical operation circuit together with data stored in the register. The result of operation is written into a desired row of the memory cell array. The memory cell array, register, and logical operation circuit are formed in the same integrated circuit, thus permitting processing such as picture element processing to be effected inside the integrated circuit, without the need to use an external data bus.

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Fujisawa, Japan

Tsutomu Minagawa