Kabushiki Kaisha Toshiba

Piolax, Inc.

Kabsuhiki Kaisha Toshiba

Tsutomu Kojima

Akio Nakagawa

Tomoko Matsudai

Takashi Koike

Takayuki Hiraoka

Ryuji Hosokawa

Hiroshi Takei

Kazunori Asano

Morio Takahashi

Akira Yamashita

Tatsuo Shiotsuki

Shinya Takashima

Kuniaki Utsumi

Kenji Honda

A semiconductor apparatus in a preferred embodiment includes: a substrate; a first chip provided on the substrate; a solder bump formed on the first chip; a solder dam arranged in substantially a rectangular and annular manner outside around the solder bump on the first chip by alternately connecting four sides and four quarter or less arcs; an electrode pad placed outside of the solder dam in the first chip; a second chip provided on the first chip in electric connection to the first chip via the solder bump; and an under-fill material filling a clearance between the first chip and the second chip inside of the solder dam. Here, a difference between an inner diameter and an outer diameter of the arc is 60 &#x3bc;m or more whereas the center radius of the arc is greater than 207.5 &#x3bc;m.

Semiconductor apparatus

A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.

Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer

There is provided with a gate drive circuit including: a first switching element connected at one end to a power terminal; a second switching element connected at one end to the other end of the first switching element and connected at the other end to a reference terminal; a gate voltage output terminal which supplies a voltage at a node between the first switching element and the second switching element to a drive switching element as an output gate voltage; a gate voltage monitoring circuit which monitors the output gate voltage; an overcurrent detection circuit which monitors a current through the drive switching element; and a control circuit which generates a control voltage for controlling impedance of the second switching element based on an on/off signal for indicating that the drive switching element should be turned on/off, a gate voltage monitoring signal and an overcurrent monitoring signal.

Gate drive circuit, semiconductor module and method for driving switching element

A securing clip for securing the first panel member with the second panel member. The securing clip, being shaped like an S-character in cross section, includes a first fitting portion for fitting a holed end portion of the first panel member, and a second fitting portion for fitting a holed end portion of the second panel member. Each of the first fitting portion and the second fitting portion is formed with an engaging pawl engaging a hole at the end portion of the corresponding panel member on an inner wall face of its own, and the second fitting portion is formed with an engagement wall engaging a regulation wall provided on the second panel member.

Securing clip

A gate driving circuit according to the present invention having, an output circuit which is connected to a first power supply terminal and a ground terminal and, upon receiving an ON/OFF signal, changes a level of a gate output terminal between a power supply voltage and a ground voltage, a shunt switching element which is connected between the gate output terminal and the ground terminal and is ON/OFF-controlled upon receiving a shunt control signal, and an output shunt control circuit which monitors the level of the gate output terminal and outputs the shunt control signal, wherein when the level of the gate output terminal decreases to not more than a first threshold value, the output shunt control circuit turns on the shunt switching element, and while the level is not more than a second threshold value larger than the first threshold value, the output shunt control circuit supplies the shunt control signal to said shunt switching element to maintain an ON state of the shunt switching element.

Gate driving circuit and semiconductor device

The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.

Semiconductor device

A resin clip includes a head for abutting on one surface of a panel upon insertion into an attachment hole thereof, a pillar extending from the center of the head, and a pair of elastic legs folded back at a tip portion of the pillar toward the head and spreading out in a V shape. Locking parts in shapes of multiple steps are formed outside the elastic leg. In addition, one side in a width direction inside the elastic leg is more protruded toward the pillar than the other side, and the pillar includes a dented portion for receiving the protruded portion.

Resin clip

A gate driver includes an edge detection circuit, an ON pulse generation circuit, first and second OFF pulse generation circuit and a status hold circuit. The first OFF pulse generation circuit generates a first OFF pulse in response to a leading or trailing edge of a control input signal, which is detected by the edge detection circuit. The status hold circuit drives an output element in response to the ON pulse outputted from the ON pulse generation circuit and holds driving status of the output element until a first OFF pulse is outputted from the first OFF pulse generation circuit. The second OFF pulse generation circuit generates a second OFF pulse in response to a protect operation signal and supplies this pulse to the status hold circuit, thereby to stop driving of the output element.

Growing community of inventors

Yokohama, Japan

Tsutomu Kojima