Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Tsutomu Kiyosawa

Yasuyuki Yanase

Atsushi Ohoka

Kazuhiro Kagawa

Chiaki Kudou

Masao Uchida

Takashi Hasegawa

Nobuyuki Horikawa

Koutarou Tanaka

Yuki Tomita

Takayuki Wakayama

Osamu Kusumoto

Kunimasa Takahashi

Haruyuki Sorada

Kazuyuki Sawada

Kouichi Saitou

Tsuneichiro Sano

Osamu Ishiyama

Daisuke Shindo

Variations in device characteristics in a plane parallel to the principal surface of a semiconductor wafer are suppressed. A semiconductor epitaxial wafer includes a semiconductor wafer and a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer and contains a first conductivity type impurity, and the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer have a positive correlation in a plane parallel to the principal surface of the semiconductor wafer.

Semiconductor epitaxial wafer, semiconductor device, and method for manufacturing semiconductor epitaxial wafer

A silicon carbide semiconductor element includes a silicon carbide semiconductor layer of a first conductivity type, a body region of a second conductivity type, a channel layer made of a silicon carbide semiconductor disposed on the silicon carbide semiconductor layer so as to be in contact with at least a part of the body region, and a gate electrode disposed on the channel layer via a gate insulating film. The channel layer has a multilayer structure of a high-concentration impurity layer containing impurities of the first conductivity type, a first medium-concentration impurity layer containing impurities of the first conductivity type, and a first low-concentration impurity layer containing impurities of the first conductivity type. The first low-concentration impurity layer is disposed closer to the body region than the high-concentration impurity layer and the first medium-concentration impurity layer.

Silicon carbide semiconductor element and method for manufacturing same

A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, and a semiconductor layer. The semiconductor layer includes a level difference for alignment mark. An epitaxial layer is disposed on a first portion of the main surface, the first portion being situated on an off-angle upstream side of the level difference, and on a second portion of the main surface, the second portion being situated on an off-angle downstream side of the level difference. A value of |WL&#x2212;WR| is 1 &#x3bc;m or less, in which WL represents a distance from a center of the level difference to a boundary between an off-angle upstream side corner portion of the level difference and a main surface or a {0001} facet plane generated on the main surface, and WR represents a distance from the center of the level difference to a boundary between an off-angle downstream side corner portion of the level difference and the main surface or the {0001} facet plane generated on the main surface.

Semiconductor device and method for manufacturing the same

A method of producing a semiconductor device includes the following steps (A), (B), and (C). In the step (A), a semiconductor epitaxial wafer is prepared. The semiconductor epitaxial wafer includes a body region. In the step (B), a channel layer is formed by epitaxial growth. In the step (C), a gate insulation film is formed on the channel layer. The channel layer contains impurity at a concentration ranging from 1&#xd7;10cmto 1&#xd7;10cm, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the steps of (B) and (C), a condition for the epitaxial growth and a condition for forming the gate insulation film are controlled so that a thickness distribution in the channel layer and a thickness distribution in the gate insulation film are positively correlated to each other.

Method of producing semiconductor device

A method of producing a semiconductor device including steps (A) and (B). Step (A) is preparing a semiconductor epitaxial wafer including a plurality of device regions, each including a body region contacting a semiconductor layer. Step (B) is forming a channel layer contacting at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer. The channel layer contains an impurity at a concentration ranging from 1&#xd7;10cmto 1&#xd7;10cm, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the step (B), a condition for the epitaxial growth is controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the impurity in the channel layer are negatively correlated to each other.

Method of producing semiconductor device for reducing variations of device characteristics within a surface of a semiconductor wafer

A semiconductor epitaxial wafer includes a semiconductor wafer, and a semiconductor layer of a first conductivity type disposed on a main surface of the semiconductor wafer. The semiconductor epitaxial wafer includes a plurality of device regions. The plurality of device regions each include a body region of a second conductivity type in contact with the semiconductor layer, a source region of the first conductivity type in contact with the body region, and a channel layer that is constituted by a semiconductor, and that is disposed on the semiconductor layer so as to be in contact with at least a part of the body region. In a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the first conductivity type impurity in the channel layer are negatively correlated to each other.

Semiconductor epitaxial wafer, semiconductor device, and method of producing semiconductor device

Semiconductor device includes semiconductor substrate, drift layer, first electrode, and second electrode. Semiconductor substrate is of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like. For example, semiconductor substrate is an n-type silicon carbide semiconductor substrate. Drift layer is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface of semiconductor substrate by epitaxial growth. Drift layer is formed of, for example, an n-type silicon carbide semiconductor. Drift layer has a thickness of t. For example, the thickness t is between about 5 &#x3bc;m and about 100 &#x3bc;m (inclusive).

Semiconductor layer is formed on semiconductor substrate. Semiconductor layer has a plurality of well regions in a surface remote from semiconductor substrate. Semiconductor layer includes drift region in addition to the plurality of well regions. The plurality of well regions each include body region, source region, and contact region. Source region is in contact with body region. Contact region is in contact with both body region and source region. Body region, source region, and source wire are at an identical potential because of contact region. Semiconductor layer includes ineffective region R at the surface remote from semiconductor substrate.

Semiconductor deviceincludes semiconductor substratedrift layerfirst electrodeand second electrodeSemiconductor substrateis of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like. For example, semiconductor substrateis an n-type silicon carbide semiconductor substrate. Drift layeris an epitaxial semiconductor layer of the first conductivity type which is formed on upper surfaceof semiconductor substrateby epitaxial growth. Drift layeris formed of for example, an n-type silicon carbide semiconductor. Drift layerhas a thickness of t. For example, the thickness t is between about 5 &#x3bc;m and about 100 &#x3bc;m (inclusive).

Semiconductor layeris formed on semiconductor substrateSemiconductor layerhas a plurality of well regionsin a surface remote from semiconductor substrateSemiconductor layerincludes drift regionin addition to the plurality of well regionsThe plurality of well regionseach include body regionsource regionand contact regionSource regionis in contact with body regionContact regionis in contact with both body regionand source regionBody regionsource regionand source wireare at an identical potential because of contact regionSemiconductor layerincludes ineffective region R at the surface remote from semiconductor substrate

A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, a semiconductor layer, and an epitaxial layer. The semiconductor layer includes a trench. Where an upstream side is an off-angle upstream side and a downstream side is an off-angle downstream side in a direction with the off-direction projected on the main surface of the substrate, a side wall of the trench includes first and second side wall portions facing each other and each crossing the off-direction of the substrate. The first side wall portion is situated closer to the off-angle upstream side than the second side wall portion.

Metal-insulator-semiconductor field effect transistor (MISFET) device and method for manufacturing the same

A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film. The first protective film covers the inner-circumferential upper source electrode, the upper gate electrode, and an inner side surface of the one or more outer-circumferential upper source electrodes except for a pad region. The second protective film covers the first protective film and at least a part of the one or more second conductivity type rings.

Silicon carbide semiconductor device

An ohmic electrode layer is disposed on a second main surface of a silicon carbide substrate, and a metal electrode layer is disposed on the ohmic electrode layer. A notch is formed along at least one pair of sides, facing each other, of a periphery of the second main surface of the silicon carbide substrate. The cross-section of the notch orthogonal to a side of the second main surface has a corner. In the cross-section, a thickness of the silicon carbide substrate at an edge thereof under which the notch is formed is smaller than a thickness of the silicon carbide substrate in a region under which the notch is not formed, and larger than a thickness of the silicon carbide substrate in a region under which a bottom of the corner is formed.

Semiconductor element, semiconductor element manufacturing method, semiconductor module, semiconductor module manufacturing method, and semiconductor package

A semiconductor device includes: a first silicon carbide semiconductor layer; a p-type first impurity region provided in the first silicon carbide semiconductor layer; and a first ohmic electrode forming ohmic contact with the p-type first impurity region. The first ohmic electrode is a silicon alloy containing nitrogen, an average concentration of nitrogen in the first ohmic electrode is higher than or equal to one half of an average concentration of nitrogen in the first impurity region, and an average concentration of a p-type impurity in a portion of the first ohmic electrode except a portion of the first ohmic electrode within 50 nm from an interface between the first ohmic electrode and the first impurity region is equal to or lower than 3.0&#xd7;10cm.

Silicon carbide semiconductor device having nitrogen-containing silicon alloy for ohmic contact to P-type impurity region

A method for manufacturing a semiconductor device includes the steps of: forming, on a principal face of a substrate, a semiconductor layer including a first semiconductor region of a first conductivity type; and forming, in the semiconductor layer, a trench having a bottom located in the first semiconductor region. The method further includes a step of forming a trench bottom impurity region being of a second conductivity type and covering the bottom of the trench by performing annealing to cause part of the semiconductor layer corresponding to an upper corner portion of the trench to move to be placed on the bottom of the trench.

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Toyama, Japan

Tsutomu Kiyosawa