Sony Corporation

Tsutomu Ichikawa

Tetsujiro Kondo

Takashi Nakamura

Naoki Kobayashi

Akira Tange

Hiroshi Sato

Yoshinori Watanabe

Yukihiro Nakamura

Hiroki Tetsukawa

Masaki Handa

Takao Inoue

Hideo Nakaya

Naoki Takeda

Akihiro Okumura

Yasunobu Node

Tsutomu Watanabe

Noriaki Takahashi

Takashi Sawao

Koji Yano

Yoshiaki Nakamura

Kazutaka Ando

Toshinobu Sugiyama

Shizuo Chikaoka

Katsuhisa Shinmei

A data access apparatus has a memory portion including plural memory banks. A data storage control portion stores the pixel data in the plural memory banks with the pixel data being divided into the plural memory banks based on information on an access pattern of plural pixels set on a predetermined screen. A data access control portion reads pixel data relative to the plural pixels specified by the access pattern at the same time from the plural memory banks at each set position in which the set position of the access pattern moves from the start position thereof toward a pixel row direction. A selector portion transmits pixel data corresponding to respective pixels constituting each of the groups of pixels based on correspondence information on input and output. Each group of pixels includes a center pixel and peripheral pixels positioned at a periphery of the center pixel.

Data access apparatus and method

An information processing apparatus includes an image taking means for taking images of a subject, a class-classification means for classifying a first image outputted by the image taking means into a class according to a characteristics thereof, a storage means for storing plural coefficient memories having different image taking conditions at the time of image taking, which store prediction coefficients according to the class acquired by learning, a designation means for designating one coefficient memory from among the plural coefficient memories based on the image taking condition when the image was taken by the image taking means, and a calculation means for calculating a second image in which noise is removed from the first image by calculating a prediction coefficient of the class of the first image, which is in the designated coefficient memory.

Information processing apparatus, information processing method, learning apparatus and learning method and program

Value-added information is created based on favorite information of a content user. The content is processed according to the generated value-added information. Favorite data indicating operations, such as fast-forward, pause, and rewind operations, performed while the content is being played back, and personal user information, such as the age group, the gender, and the life-style, of the content user are transferred to a server via a network. The server performs statistical processing on the user favorite data to generate value-added information according to the attributes of the user, such as the age group, the gender, and the life-style. Accordingly, the user is able to search for popular titles, play back only popular scenes, and skip uninteresting scenes by using a content playback apparatus.

Content processing apparatus and content processing method for digest information based on input of content user

Content processing apparatus and content processing method for digest information based on input of a content user

The invention relates to a memory device and the like. The memory device comprises one or more memory block. The memory block has a memory cell array consists of multiple memory cells () arranged in a matrix form. A region of the multiple memory cells () includes multiple divisional domains (-) divided in the direction along word line (WL). Each of the word lines (WL) has multiple divisional selection lines (WLa-WLe) divided corresponding to the multiple divisional domains. The memory block has a switching mechanism () for switching the divisional word lines (WL) that are to be simultaneously activated in each of the divisional domains. Multiple memory cells () associated with each of the divisional word lines store a horizontal or vertical array of pixel data. The inventive memory device enables simultaneous access to multiple items of pixel data constituting a pixel block having an arbitrary configuration.

Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device

A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage controller (), data read controllerand data move controller (), for judging, based on an access pattern representing a plurality of desired data to be read simultaneously when storing data sequentially into the memory with the data being divided among the plurality of memory banks of the memory, whether the data going to be stored are ones at locations corresponding to the access pattern, and storing all data at the locations corresponding to the access pattern into different memory banks by skipping a memory bank in which the data is to be stored, by incrementing its address, when the data to be read simultaneously are ones at the locations corresponding to the access pattern, and storing data at the locations corresponding to the access pattern into the memory bank having the bank address thereof incremented. The memory controlling means provides a control to read a plurality of desired data simultaneously from a memory ().

Data storage unit, data storage controlling apparatus and method, and data storage controlling program

A data storage device includes a memory including a plurality of memory banks, a data storage processor that initially arranges data in the plurality of memory banks based on an access pattern including a plurality of desired pixels of data to be read simultaneously so as to store pixels of data between access candidates constituting the access pattern in an identical memory bank, and a data read and storage processor that reads the data initially arranged in the plurality of memory banks of the memory. The data read and storage processor reads a pixel of data from a memory bank, and stores the read pixel of data in a memory bank in which pixels of data in an adjacent range defined in ranges, which are defined by locations of the access candidates of the access pattern, based on a direction in which the access pattern is moved.

Data storage device, data storage control apparatus, data storage control method, and data storage control program

An active matrix display device includes a pixel array unit having pixels arranged in a matrix pattern, a scanning circuit which sequentially selects pixels in unit of rows, and a signal circuit which receives a video signal containing serial dot data corresponding to each pixel and which writes the dot data into a selected pixel. The signal circuit receives a video signal which includes dot data corresponding to pixels to be rewritten but does not include dot data corresponding to pixels not to be rewritten and which includes skip data defining a skip amount. The signal circuit sequentially processes the dot data and skip data so as to write the corresponding dot data into pixels to be rewritten by skipping pixels not to be rewritten based on the skip data.

Active matrix display device, video signal processing device, method of driving the active matrix display device, method of processing signal, computer program executed for driving the active matrix display device, and storage medium storing the computer program

A semiconductor device and an image data processing apparatus are capable of easily realizing address control, simplifying a circuit for address control, and easily realizing access to image data while reducing the volumes of pieces of image data of different resolutions in different hierarchies. In the image data processing apparatus, a memory cell array stores pieces of composite data, each containing a piece of pixel data and additional information data, for example, a motion vector associated with the pixel data. A designated pixel data and a motion vector associated with the pixel data are read out and a search region is suitably predicted and set up on the basis of the motion vector, and motion estimation is performed in the search region, for example, by a block matching process. Accordingly, motion estimation can be performed in a small search region equivalent to a large search region having been generally used for motion estimation, to realize high-speed, high-efficient motion estimation and improve the estimation accuracy.

Semiconductor device, image data processing apparatus and method

A column address is decoded by each column decoder, and an arrangement of pixels to be written to a memory cell array is rotated by a rotation circuit. The rotation result is written to the memory cell array in accordance with the decoding result of the column address. Then, the column address is decoded by each column decoder to a decoding result which is different from the decoding result of the column address at the time of writing. In accordance with the decoding result, pixels stored in the memory cell array are read. The arrangement of the read pixels is rotated by the rotation circuit and then outputted. Thus, rearrangement of pixels constituting an image can be carried out quickly while avoiding any increase in the size of the device.

Data processing device and data order converting method

A semiconductor memory device having an internal constant voltage source in which a charge pumping circuit generates a boosted voltage, wherein by using a constant voltage drop circuit or a voltage follower which outputs a voltage following a reference voltage, a voltage adjusted to a minimum operating voltage of the memory cells or a voltage near to the minimum operating voltage is supplied to the word lines during activation.

Semiconductor memory device having stabilizing circuit of word line

A protective circuit for a semiconductor integrated circuit having a MOS transistor is constructed of a protective device having a first conducting type of protective device region provided in the surface of a substrate and a second conducting type of first diffused part and second diffused part provided in the surface of the protective device region. The first diffused part is connected to a power line of the MOS transistor, and the second diffused part is connected to a signal line between an external input terminal and the MOS transistor. The bipolar operation of the protective device allows electric charge accumulated in the power line to be discharged from the external input terminal, and also allows electric charge accumulated in the external input terminal to be discharged from the power line. Accordingly, the occurrence of electrostatic breakdown in the semiconductor integrated circuit can be prevented.

Protective circuit for semiconductor integrated circuit

In an integrated circuit card having memory therein, an address detecting circuit and a power supply circuit are provided and the output voltage from the power supply circuits is changed based on address data and supply to a part of the memory, so as to improve the use efficiency of an internal power supply.

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Kanagawa, Japan

Tsutomu Ichikawa