Renesas Electronic Coporation

Tsutomu Himukai

Takashi Ogura

Masashige Moritoki

Takamasa Itou

Shigeaki Shimizu

To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M&#x3e;N), capacitance elements are provided over the interconnect layers comprised of (M&#x2212;N) layers or (M&#x2212;N+1) layers.

Growing community of inventors

Kanagawa, Japan

Tsutomu Himukai