Oki Electric Industry Co., Ltd.

Tsutomu Higuchi

Hitoshi Yamada

A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Memory macro with modular peripheral circuit elements

Memory macro with modular peripheral circuit elements having a number of line drivers selectable based on number of memory blocks

A semiconductor memory device comprises memory banks each including a memory cell array and a control circuit for the memory cell array and an interface circuit shared by the plural memory banks. The semiconductor memory device is adapted for performing reading of data from the plural memory banks and rewriting of data to the memory banks. In an operation mode for performing the reading, processings Ato Aare performed. In an operation mode for performing the rewriting, processings Bto Bare performed.

Semiconductor memory device

A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated-circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

A voltage supply circuit supplies an operational voltage to plural sense amplifier arrays and includes a plurality of MOS transistors. Each transistor is located between a power supply and one sense amplifier array. A stable operational voltage is supplied to the sense amplifier circuits in each sense amplifier array, whereby a high speed operation is realized.

Voltage supply circuit in a semiconductor memory device

A semiconductor device includes a protection circuit and a guard ring. The guard ring is formed between a MOS transistor of a semiconductor substrate and internal circuits, to cut off a leak current from the MOS transistor to the internal circuits. The guard ring includes a well region and a pair of heavily doped impurity regions for med spaced apart from each other on the surface of the well region. The pair of doped regions have mutually different conductivity types and have substantially equal voltages applied to have potentials with respect to the source of the MOS transistor. There are formed a first parasitic transistor having one heavily doped impurity region as the collector, the semiconductor substrate as the base, and the drain of the MOS transistor as the emitter, the one heavily doped impurity region being identical in conductivity type with the well region; and a second parasitic transistor having the other heavily doped impurity region as the emitter, the well region as the base, and the semiconductor substrate as the collector. When the first parasitic transistor conducts, the second parasitic transistor conducts, which turns off the first parasitic transistor. Thus, the leak current is prevented from flowing from the MOS transistor through the first parasitic transistor to the internal circuits.

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Tokyo, Japan

Tsutomu Higuchi