Hitachi, Ltd.

Tsutomu Goto

Takehisa Hayashi

Akira Yamagiwa

Kenichi Ishibashi

Tsuyoshi Watanabe

Hideki Murayama

Naoki Hamanaka

Satoshi Yoshizawa

Toshiro Takahashi

Toshitsugu Takekuma

Masabumi Shibata

Yasuhiro Ishii

Hiroshi Yashiro

Kimitoshi Yamada

Toru Horimoto

Masahiko Yamauchi

Akira Kito

Tatsuhiro Aida

Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.

Apparatus for interconnecting logic boards

A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

Semiconductor integrated circuit system having function of automatically

In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.

Simultaneous bidirectional transmission circuit

A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer. At least one of the plurality of computers includes a request message queue for storing a coherence control request message issued by the coherence control execution command when the coherence control designation command is executed. The coherence control designation command includes data for designating the order of reading/changing the shared data, and the request message queue includes a counter for storing a current state regarding the control of the order of reading/changing the shared data and a unit for storing a value regarding the control of the order of reading/changing the shared data.

Distributed shared data management system for controlling structured

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Yokohama, Japan

Tsutomu Goto