Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Tsutomu Fujii

Shinichiro Imura

Yoshifumi Taguchi

Hiromasa Fukazawa

Kozue Kuniyoshi

Yukihiro Shimasaki

Morio Tomiyama

Kazuya Hisada

Mitsuo Saitoh

Hitoshi Ishimoto

Satoshi Maeshima

Kazuya Yamasaki

Mitsuo Yoshimura

Tsutomu Kawashima

Takeshi Minamiura

Motohiro Sakata

Masashi Morita

Miyuki Yoshimoto

Junichi Shimada

Hideki Yamashita

Takuya Yasui

Nobuyuki Kamikihara

Chiho Nobumori

Hirofumi Miyashita

Takeya Fujino

Nobuyuki Iwauchi

Yoko Kasai

Hidenori Shibata

Tatsuo Gou

Toshihiro Otsuka

Yasumichi Yoshihara

A fuel cell module that suppress deterioration of an electrolyte membrane is provided. The fuel cell module includes a membrane-electrode assembly (MEA) including a polymer electrolyte membrane, an anode catalyst layer disposed on a surface of the membrane, a cathode catalyst layer disposed on the other surface of the membrane, and a pair of gas diffusion layers laminated on the anode catalyst layer and the cathode catalyst layer respectively, a pair of separators sandwiching the MEA; and a sealing member sealing the MEA and each of the pair of separators together. One gas diffusion layer and the sealing member overlaps in a thickness direction within a region including a center-side edge of the sealing member, and the one gas diffusion layer is notched through in the thickness direction at a part of a portion corresponding to the region.

Fuel cell module, fuel cell stack, and manufacturing method of fuel cell module

A fuel cell includes: an electrolyte membrane; a cathode positioned on a first surface of the electrolyte membrane; an anode positioned on a second surface of the electrolyte membrane; a cathode-side sealant positioned on a surface of the cathode different from the electrolyte membrane side of the cathode; an anode-side sealant positioned on a surface of the anode different from the electrolyte membrane side of the anode; a cathode-side separator positioned on a surface of the cathode-side sealant different from the cathode side of the cathode-side sealant; and an anode-side separator positioned on a surface of the anode-side sealant different from the anode side of the anode-side sealant. The anode-side separator has a projection on a surface stacked on the anode-side sealant, or the cathode-side separator has a projection on a surface stacked on the cathode-side sealant.

Fuel cell

Provided is a fuel cell catalyst layer including: a fibrous carbon material; catalyst particles; a particulate carbon material; and a proton-conductive resin, wherein a region A including at least the fibrous carbon material in a state of an agglomerated body and a region B including at least the catalyst particles, the particulate carbon material, and the proton-conductive resin are formed, the region A being disposed in an island form in the region B.

Fuel cell catalyst layer, membrane electrode assembly, and fuel cell

An assembly, including: an electrolyte membrane; and a frame that holds the electrolyte membrane, wherein the frame includes a first frame that holds one surface of the electrolyte membrane, and a second frame that holds the other surface of the electrolyte membrane, the frame further has a joint part that joins the first frame and the second frame, and the joint part has a projection.

Assembly, fuel cell using same, and method of disassembling same

Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern () is formed in relatively narrow wiring void (Area_S) so as to extend in a direction different from that of dummy patterns () formed in relatively wide wiring void (Area_S).

Semiconductor device

An optical information recording medium includes a disc-shaped substrate, at least one information recording layer formed over a recording/reproducing-side main surface of the substrate, a light transmitting layer formed over the information recording layer, and a protecting layer formed to cover the light transmitting layer and at least one part of a side end surface perpendicular to the main surface of the substrate. At least the part of the side end surface is covered with the protecting layer for covering the recording/reproducing-side main surface, and the surface of the protecting layer covering at least the part of the side end surface has a larger surface roughness than that of the surface of the protecting layer covering the upper of the recording/reproducing-side main surface.

Optical information recording medium and method for manufacturing optical information recording medium

The present invention provides a front panel for a plasma display panel which can suppress the incidence of chipping of the barrier rib of a rear panel for a PDP, can enhance the stability of initial electron emission in a dielectric layer, and can reduce a voltage required for maintaining a wall charge. The front panel for a plasma display panel includes a substrate, a plurality of electrodes formed on the substrate, a dielectric layer formed to cover the respective electrodes and the substrate, a dielectric-protection layer formed to cover the dielectric layer, and powder components dispersed on the dielectric-protection layer, wherein an annealed layer having a thickness of 10 to 300 nm is formed on at least the exposed surface of each of the powder components, wherein said exposed surface does not contact the dielectric-protection layer.

Front panel for plasma display panel and method for producing the same

Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.

Method for designing semiconductor integrated circuits having air gaps.

Growing community of inventors

Osaka, Japan

Tsutomu Fujii