Intel Corporation

Tsung-Yung Chang

Stefan Rusu

Kevin X Zhang

Fatih Hamzaoglu

Jonathan Shoemaker

Ming Chieh Huang

In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

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Cupertino, CA, United States of America

Tsung-Yung Chang