Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsung-Yung Chang

Chiting Cheng

Hung-Jen Liao

Mahmut Sinangil

Atul Katoch

Ching-Wei Wu

Kao-Cheng Lin

Ming-Hung Chang

Saman M I Adham

Hao-I Yang

Donald George Mikan, Jr

Ming-Chien Tsai

Uppu Sharath Chandra

Chia-En Huang

Cheng Hung Lee

Chia-en Huang

Wei-Jer Hsieh

Chien-Kuo Su

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

Scan synchronous-write-through testing architectures for a memory device

In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.

Pre-charging bit lines through charge-sharing

In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.

Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.

SPSRAM wrapper

Growing community of inventors

Hsinchu, Taiwan

Tsung-Yung Chang