Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Lextar Electronics Corporation

Tsung-Yu Yang

Chung-Jen Huang

Yun-Chi Wu

Cheng-Bo Shu

Chung-Long Chang

Po-Wei Liu

Yu-Wen Tseng

Jing-Ru Lin

Hung-Ling Shih

Chih-Ping Chao

Kuan-Chi Tsai

Chien Hung Liu

Wei-Kung Tsai

Jui-Yu Pan

Kuo-Yu Cheng

Yueh-Chieh Chu

Keng-Yu Chen

Cheng-Chieh Hsieh

Chun-Hung Chen

Hung-Chi Li

Yu-Chun Chang

Josh Lin

Ching-Chung Hsu

Tsung-Hua Yang

Che-Yung Lin

Grace Chang

Chun-Hong Chen

Chen-Yao Tang

Yu Hung Chen

Chia-Ta Hsieh

Tzong-Liang Tsai

Alex Kalnitsky

Te-Chung Wang

Ping-Cheng Li

Po-Hsun Wu

Yong-En Syu

Chien-Yi Lee

Shih-Jung Tu

Yung-Chih Tsai

Shih-Chang Liang

Nai-Wei Hsu

Min-Rong Chen

Jun-Hong Guo

Jih-Chieh Lee

Chia-Lin Hsiao

Yu-Sheng Tseng

Yung-Chun Tu

A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Semiconductor structures and manufacturing method thereof

A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Semiconductor arrangement including first and second gate electrodes and method of manufacture

A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Deep trench isolation structure and method of making the same

A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Method for eliminating divot formation and semiconductor device manufactured using the same

A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Semiconductor arrangement and method for making

Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate

Semiconductor arrangement and method of manufacture

Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a 'T'-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.

BCD device layout area defined by a deep trench isolation structure and methods for forming the same

A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Semiconductor isolation structure and method of making the same

Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region

A contour accuracy measuring system and a contour accuracy measuring method are provided. The contour accuracy measuring system captures location coordinate data of shafts of a machine tool. The location coordinate data are calculated to obtain a first true round trajectory on an inclined plane as reference information. The contour accuracy measuring system then adjusts parameters of the locations of the shafts based on the location coordinate data of the shafts of the reference information to generate a second true round trajectory on the inclined plane, so as to get to know whether the locations of the shafts after the parameters are adjusted comply with a standard. Therefore, the overall measurement process can be speeded up by automatically measuring the parameters and automatically testing an operating status.

Contour accuracy measuring system and contour accuracy measuring method

Growing community of inventors

Tainan, Taiwan

Tsung-Yu Yang