United Microelectronics Corp.

National Yang Ming Chiao Tung University

Tsung-Yin Hsieh

Tzu-Hao Fu

Chih-Sheng Chang

Kun-Chen Ho

Shih-Chun Tsai

Ci-Dong Chu

Yi-How Chou

Yang-Chou Lin

Home-Been Cheng

En-Chiuan Liou

Ssu-I Fu

Yu-Ping Wang

Chi-Mao Hsu

Chien-Chung Huang

Chih-Wei Yang

Nien-Ting Ho

Chien-Ming Lai

Yu-Ru Yang

Yi-Wen Chen

Chia-Fu Hsu

Ya-Huei Tsai

Jian-Cun Ke

Yu-Ting Tseng

Hao-Chiao Hong

Hung-Yi Wu

Yu-Feng Liu

A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Metal interconnect structure having cap layer with different thicknesses and method for fabricating the same

A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.

Metal interconnect structure and method for fabricating the same

A structure of semiconductor device includes a substrate. A first dielectric layer is disposed over the substrate, wherein the first dielectric layer has an air trench. A plurality of trench metal layers is disposed in the first dielectric layer, wherein the air trench is between adjacent two of the trench metal layers and without contacting to the trench metal layers. A liner layer is disposed on the first dielectric layer to cover the trench metal layers and a profile of the air trench. An etching stop layer is disposed on the liner layer, wherein the etching stop layer seals the air trench to form an air gap between the adjacent two of the trench metal layers.

Semiconductor device and method for fabricating the same

A patterning method includes the following steps. A layout pattern is provided to a computer system. The layout pattern includes stripe patterns, and each of the stripe patterns extends in a first direction. Mandrel patterns are formed corresponding to a part of the stripe patterns. Each of the mandrel patterns extends in the first direction. A modification is performed to the mandrel patterns for elongating at least a part of the mandrel patterns in the first direction. Ends of the mandrel patterns in the first direction are aligned in a second direction perpendicular to the first direction after the modification. The mandrel patterns are outputted to a photomask after the modification. A photolithography process using the photomask is performed for forming a patterned structure on a substrate. By performing the modification to the mandrel patterns, design flexibility of the layout pattern corresponding to the patterning method may be enhanced.

Patterning method

A method for forming patterns for semiconductor device includes following steps. A substrate including a hard mask layer and a sacrificial layer is provided. A plurality of mandrel patterns are formed on the substrate. A spacer is respectively formed on sidewalls of the mandrel patterns. The mandrel patterns are removed to form a plurality of spacer patterns directly formed on the sacrificial layer. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion of the first blocking layers are formed on the substrate. The sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers, and the second blocking layers serving as etching masks to form a patterned hard mask layer on the substrate.

Method for forming patterns for semiconductor device

A method for forming patterns for semiconductor device includes following steps. A substrate is provided. The substrate includes a hard mask layer and a sacrificial layer formed thereon. A plurality of spacer patterns parallel with each other are formed on the substrate. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion the first blocking layer are formed on the substrate after forming the first blocking layer. Next, the sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers and the second blocking layer being used as etching masks to form a patterned hard mask layer on the substrate.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

A successive approximation (SA) analog-to-digital converter (ADC) capable of estimating its own capacitance weight errors includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same

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Tainan, Taiwan

Tsung-Yin Hsieh