Macronix International Co., Ltd.

Industrial Technology Research Institute

Mediatek Corporation

Tsung-Yi Chou

Chyi-Ming Leu

Chun-Yi Yang

Hsien-Kuang Lin

Te-Yi Chang

Wen-Hua Chang

Sue-May Chen

Jauder Jeng

Shih-Fu Huang

Zong-Qi Zhou

Ying-Tsai Ting

Shang-Ping Lin

Che-Chin Wu

Ming-Feng Zhou

Chung-Yi Li

Loen-Shien Tsai

Hsiang-Pang Lee

A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Test method for memory

A current amplifier and a transmitter using the same. The current amplifier includes: a first transistor having a gate coupled to a former-stage circuit, a drain coupled to a current source, and a source biased at a constant voltage level; a second transistor having a gate coupled to the current source and having a source and a drain; a first impedance circuit coupled between the gate of the first transistor and the source of the second transistor; and a second impedance circuit coupled between the source of the second transistor and a ground terminal. The current amplifier receives an input current from the former-stage circuit and generates an output current at the drain of the second transistor. Note that no current source is connected to the source of the first transistor.

Current amplifier and transmitter using the same

A photosensitive composition and a photoresist are provided. The photoresist is formed by compounding a photosensitive composition. The photosensitive composition comprises a binder agent, a photomonomer and a photoinitiator. The binder agent has a chemical structure comprising following repeating unit: Ris H or CH, n is 2-40 of integer. The photomonomer has an amount of about 25-95 parts by weight relative to 100 parts by weight of a solid content of the binder agent. The photo initiator has an amount of about 0.5-15 parts by weight relative to 100 parts by weight of the solid content of the binder agent.

Photosensitive composition and photoresist

A reading method of a memory is provided. The memory has a turn on window. The reading method comprises the following steps. A reading voltage is provided. The reading voltage is shown if the reading voltage is located in the turn on window. The reading voltage is updated by moving a predetermined distance if the reading voltage is not located in the turn on window. The predetermined distance is cut by half before the step of updating the reading voltage is performed again.

Reading method of memory

A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.

Accessing method and a memory using thereof

The disclosure provides a white coating composition, and a device employing a coating made of the composition. The white coating composition includes 20-55 parts by weight of silicon dioxide particles, 40-75 parts by weight of inorganic material, and 5-40 parts by weight of silsequioxane, wherein the silsequioxane is prepared from monomers comprising a first monomer represented by the Formula (I) and a second monomer represented by the Formula (II) 

White coating composition, and device employing coating made therefrom

The invention provides a method for reading a first data storage of a memory cell. The method comprises sensing a first current of the memory cell by applying a first bit line voltage on the memory cell. When the first current is larger than a first reference current with respect to the first bit line voltage, the first data storage is determined to be at an un-programmed state. Otherwise, a second current of the memory cell is sensed by applying a second bit line voltage on the memory cell. When the difference between the first current and the second current is larger than the difference between the first reference current and the second reference current, the first data storage is determined to be at the un-programmed state. Otherwise, the first data storage is determined to be at a programmed state.

Memory apparatus and method for operating the same

A memory apparatus and a method thereof for operating a memory are provided herein. The apparatus has the memory and a controller. The memory has a plurality of memory cells, and each the memory cells has a first side and the second side. Each of the first side and the second side is programmable to store one bit of data. The controller programs the first sides and the second sides of the memory cells to different levels. Several threshold voltage distributions of the programmed memory cells could be overlapped with each other. The controller distinguishes the bits of the memory cells by comparing the threshold voltages of the memory cells with the different levels and by comparing the threshold voltages with those of neighbor sides.

Memory apparatus and method thereof for operating memory

A method of fabricating a mask ROM is provided, gate dielectric and a plurality of first conductive strips are sequentially formed over a substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with corresponding first wells and form a diode memory cell array. Additional diode memory cell arrays may stack over the diode memory cell array to increase device integration.

Growing community of inventors

Hsinchu, Taiwan

Tsung-Yi Chou