Advanced Semiconductor Engineering, Inc.

Iris Optronics Co., Ltd.

Tsung-Ming Pai

Chi-Chang Liao

Kuang-Hui Chen

Meng-Hui Lin

Pao-Hei Chang Chin

Chung-Hao Lee

Shu-Shien Liu

Fu-Ming Wang

Song-Fei Wang

Sung-Fei Wang

Shin-Shyan Hsieh

Chih Min Pao

A cholesteric liquid crystal writing board, which can display a writing track, includes a cholesteric liquid crystal device, an optical layer, a photo-sensing array and a voltage control circuit. The cholesteric liquid crystal device includes plural liquid crystal control areas. The optical layer has plural optical openings. The photo-sensing array includes plural photo sensors arranged in an array. The photo sensors are disposed corresponding to the optical openings. One of the photo sensors senses a luminous flux change and generates an erasing signal accordingly. The voltage control circuit receives the erasing signal and outputs a voltage signal accordingly to the liquid crystal control areas corresponding to the photo sensors having the luminous flux change, such that a part or all of cholesteric liquid crystals corresponding to the liquid crystal control areas are morphologically changed so as to clear a part or all of the writing trace.

Cholesteric liquid crystal writing board

A cholesteric liquid crystal writing board comprises a cholesteric liquid crystal device, a photo-sensing array layer and a mode control unit. The photo-sensing array layer is disposed at one side of the light-emitting surface of the cholesteric liquid crystal device. The photo-sensing array layer comprises a plurality of gate control lines and a plurality of mode control lines. The mode control unit comprises a main control circuitry and a plurality of mode switches coupled to the main control circuitry. Each mode switch is coupled to one of the mode control lines correspondingly. The gate control lines intersect with the mode control lines so as to define a plurality of light sensing areas arranged in an array. Each light sensing area has a switch element and a light-sensing element. The main control circuitry controls each mode switch to be switched between a voltage output mode and a voltage write mode.

A flip-chip package is described. The flip-chip package includes a chip, a substrate, supporters and electrically conductive adhesive bumps. The electrically conductive adhesive bumps are located between the chip and the substrate electrically connecting the bonding pads on the former and the bump pads on the latter, wherein each electrically conductive adhesive bump has a smaller diameter at the central portion thereof than at the end portions thereof. The supporters are also disposed between the chip and the substrate surrounding the active area of the chip, so that the chip can be supported on the substrate.

Flip-chip package and fabricating process thereof

The present invention relates to a stacked semiconductor chip package comprising a substrate, a first chip, a plate, and a second chip The first chip is mounted on the substrate. The second chip comprises two opposed longitudinal sides defining a first length. The plate is mounted between the first chip and the second chip, and connects the first chip and the second chip. Corresponding to the two longitudinal sides of the second chip, the plate has two opposed longitudinal sides defining a second length. The second length is larger than the first length to expose the opposed longitudinal sides of the plate. An overflow adhesive portion is formed between the plate and the second chip, and the overflow adhesive portion exposes on the plate. Therefore, the testing instrument can detect the size of the overflow adhesive portion and the thickness of the adhesive layer so as to control the quality of the stacked semiconductor chip package. The adhesion strength between the stacked chip and the plate can be augmented to raise the reliability of the stacked semiconductor chip package product.

Stacked semiconductor chip package

A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.

Method for fabricating a stacked chip package

A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

Method for fabricating stacked chip package

A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface, of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step the cycle time may be reduced thereby cutting down the production cost.

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Tainan, Taiwan

Tsung-Ming Pai