Mediatek Corporation

Realtek Semiconductor Inc.

Mediatek Singapore Pte. Ltd.

Tsung-Ming Chen

Chia-Hsin Wu

Sang Won Son

Yuan-Hung Chung

Bo-Shih Huang

Cheng-Yu Liu

Ti-Ku Yu

Wei-Chia Chan

Shih-Chieh Yen

Shawn Min

George Chien

Ching-Chia Cheng

Yu-Hsien Chang

Yi-Jang Wu

Yi-An Li

Yi-Chu Chen

Wei-Kai Hong

Yu-Ming Lai

Chieh-Yuan Hsu

A clock generating circuit includes a control circuit and a phase interpolator. The control circuit converts an input signal to generate an encoded signal having multiple bits and adjusts arrangement of the bits according to a pointer to generate a control signal having multiple control bits. The phase interpolator includes a first driving circuit, a second driving circuit and an output terminal configured to output an interpolated clock signal. The first driving circuit receives a first clock signal and includes multiple first driving units that are turned on or off to drive the first clock signal in response to multiple first control bits in the control bits. The second driving circuit receives a second clock signal and includes multiple second driving units that are turned on or off to drive the second clock signal in response to multiple second control bits in the control bits.

Clock generating circuit and method for generating clock signal

The present invention discloses a signal output circuit applying bandwidth broadening mechanism for an image signal transmission apparatus that includes a first driving circuit and a second driving circuit. The first driving circuit includes a continuous time linear equalizer (CTLE) and is configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a first output signal, in which a zero point and two poles of a frequency response of the first driving circuit are determined by circuit parameters thereof. The second driving circuit is configured to receive and amplify the first output signal to generate a second output signal for an image receiving apparatus.

Image signal transmission apparatus and signal output circuit applying bandwidth broadening mechanism thereof

A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.

Apparatus and method for calibrating characteristics of power amplifier in transmitter

Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Open loop fractional frequency divider

A current mode logic buffer device for suppressing electromagnetic interference includes two output ports and three or more sets of current mode logic buffers. First, second, and third current mode logic buffers respectively generate first, second, and third clock signals in response to first, second, and third differential input signals. The second differential input signal is delayed by a time difference from the first differential input signal, and the third differential input signal is delayed by the time difference from the second differential input signal. The output ports receive the first clock signal, the second clock signal, and the third clock signal, and output a full clock signal. A signal generating method for suppressing electromagnetic interference is also provided.

Current mode logic buffer device for suppressing electromagnetic interference and signal generating method thereof

An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.

ESD protection circuit

An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line, wherein no ESD current flows through the impedance device when an ESD event occurs at the pad.

A transceiver includes a power amplifying circuit, a first balance-unbalance circuit, a switchable matching circuit, and a low-noise amplifying circuit. The power amplifying circuit generates differential output signals during a transmitting mode of the transceiver. The first balance-unbalance circuit converts the differential output signals into a single-ended output signal. The switchable matching circuit receives the single-ended output signal on a signal port of the transceiver during the transmitting mode, and converts a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver. The low-noise amplifying circuit converts the single-ended input signal into a low-noise input signal during the receiving mode.

Transceiver and related switching method applied therein

A signal transceiver includes a first power amplifier coupled to a chip output port of a chip; an impedance transforming circuit; a switching circuit arranged to selectively couple the chip output port to a first port of the impedance transforming circuit; and a receiving amplifier coupled to a second port of the impedance transforming circuit.

Signal transceiver

A transceiver includes: a power amplifying circuit arranged to generate differential output signals during a transmitting mode of the transceiver; a balance-unbalance circuit arranged to convert the differential output signals into a single-ended output signal; a switchable matching circuit arranged to receive the single-ended output signal on a signal port of the transceiver during the transmitting mode, and to convert a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver; and a low-noise amplifying circuit arranged to convert the single-ended input signal into a low-noise input signal during the receiving mode. The power amplifying circuit, the Balun, the switchable matching circuit, and the low-noise amplifying circuit are configured as a single chip.

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Hsinchu, Taiwan

Tsung-Ming Chen