United Microelectronics Corp.

Tsung-Min Kuo

Chun-Mao Chiou

Shyan-Liang Chou

Po-Wen Su

Po-Jui Liao

Jie-Ning Yang

Ti-Bin Chen

Yao-Chang Wang

Chi-Sheng Tseng

Feng-Mou Chen

Chun-Chieh Fang

Po-Jong Chen

A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.

Semiconductor structure having trimming spacers

A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.

Method of trimming spacers and semiconductor structure thereof

A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Resistor integrated with transistor having metal gate

Resistor and manufacturing method thereof

A semiconductor process is provided. First, a substrate having a dielectric layer formed thereon is provided. Thereafter, an interconnection structure including copper is formed in the dielectric layer. Afterwards, a metal layer is formed on the dielectric layer. The metal layer is then patterned to form a pad. An annealing process is performed, wherein the gas source for the annealing process includes hydrogen in a concentration of 50% to 90%.

Semiconductor process

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Tainan, Taiwan

Tsung-Min Kuo