Taiwan Semiconductor Manufacturing Comp. Ltd.

Silicon Integrated Systems Corporation

Mediatek Corporation

Aver Information Inc.

Tsung-Lin Lee

Feng Yuan

Chih Chieh Yeh

Chang-Yun Chang

Yen-Ming Chen

Wei-Jen Lai

Hung-Li Chiang

Cheng-Yi Peng

Chih-Hao Chang

Chih-Chieh Yeh

Hung-Ming Chen

Tzung-Yi Tsai

Yu-Lin Yang

Chia-Cheng Ho

Kuan-Jung Chen

Clement Hsingjen Wann

Chih-Hsin Ko

Jeff J Xu

Jiunn-Ren Hwang

Tzyh-Cheang Lee

Chao-Ching Cheng

Wen-Chih Chiang

Jung-Piao Chiu

Cheng-Hung Wang

Fu-Liang Yang

Shao-Ming Yu

Yi-Hsiu Liu

Yee-Chia Yeo

Tzu-Chiang Chen

Shiuan-Jeng Lin

Chun-Ming Lin

Huicheng Chang

Liang-Yin Chen

Da-Wen Lin

Wei-Ting Chien

Chin-Hsiang Lin

Feng-Cheng Yang

Wei-Yang Lee

Cheng-Hsien Wu

Shih-Chieh Chang

Chih-Sheng Chang

I-Sheng Chen

Wei-Sheng Yun

Sey-Ping Sun

Zheng-Yang Pan

Yi-Ming Lin

Chao-An Jong

Choh Fei Yeap

Chih-Hung Yeh

Ching-Yu Chang

Shahaji B More

Gerben Doornbos

Tung Ying Lee

Dian-Hau Chen

Chun-Chieh Wang

Ming-Feng Shieh

Georgios Vellianitis

Mark Van Dal

Yen-Ting Chen

Yi-Min Huang

Chen-Nan Yeh

Meng-Hsuan Hsiao

Hsin-Chih Chen

Tsung-Chieh Hsiao

Hung-Lin Chen

Po-Kang Ho

Chung-Ming Lin

Zi-Yuang Wang

Johnson Chen

Chung-Ju Lee

Ping-Wei Wang

Chia-Fu Lee

Han-Ting Tsai

Ming-Shuan Li

Fang-Shi Jordan Lai

Ming-Shiang Lin

Chiu-Hua Chung

Sheng-Chun Yang

Tung-Ching Tseng

Tang-Xuan Zhong

Chia-Sheng Peng

Sheng-Da Liu

Wesley Lin

Yu-Shine Lin

Yu-Ting Liu

Rong-Liang Chiou

Chih-Hsin Yang

Jui-Hsuan Chiang

Che-Yu Chiang

Sheng Chi Lin

Chung-Hsien Tsai

Yu-Chin Chou

Wei-Hsiao Wang

Hsin-Yen Lee

Chih-Hsin Tsao

Bor-Wen Lai

Tzu-Hao Yeh

Ting-Ming Yang

Choh-Fei Yeap

A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Multi-gate device and related methods

Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Device and method of fabricating multigate devices having different channel configurations

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Method for fabricating a strained structure and structure formed

A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.

Liner structures

The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

FinFET structure with a composite stress layer and reduced fin buckling

A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

Semiconductor structure and method for forming the same

A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Communication receiver using multi-stage channel equalization and associated method

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Semiconductor devices and methods of fabricating the same

Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Bipolar junction transistor (BJT) and fabricating method thereof

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

Structure and formation method of semiconductor device structure with nanowires

A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.

Performing annealing process to improve Fin quality of a FinFET semiconductor

Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

Structures and methods for trench isolation

Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Structures and methods for reducing process charging damages

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Gate spacer structure and method of forming same

Growing community of inventors

Hsinchu, Taiwan

Tsung-Lin Lee