Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Tsung-Hung Lee

Shih-Hao Lin

Chien-Chih Lin

Szu-Chi Yang

Ka-Hing Fung

Kuang-Yuan Hsu

Yen-Ting Chen

Chien-Tai Chan

Chun-Fu Cheng

Hsien-Chin Lin

Wen-Kai Lin

Ming-Lung Cheng

Shih-Syuan Huang

Han-Pin Chung

Hung-Kai Chen

Hsiao-Chung Cheng

Chun Hsiung Tsai

Yu-Lien Huang

Chih Chieh Yeh

Tsz-Mei Kwok

Da-Wen Lin

Chun-Hsien Lin

Chao-Ching Hsu

Chih-Liang Pan

Tsai-Yu Huang

Kai-Yuan Siao

Po-Kai Hsiao

Mao-Rong Yeh

Jian-Feng Li

Chien-Chih Lee

Allen Chien

Cin-Shun Chen

Cheng-Ting Ding

In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Semiconductor device and method

The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Interface trap charge density reduction

First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

Doping for FinFET

A gate output control method is adapted into a flat display having a plurality of gate drive integrated circuits. The method comprises: providing a gate control signal; providing a oblique control signal to oblique modulate the gate control signal for generating a gate control signal with oblique; modulating the gate control signal with oblique to obtain a modulated gate control signal; and outputting the modulated gate control signal to the gate drive integrated circuits. A falling edge of the modulated gate control signal comprises a oblique-varying period and a vertical-varying period. In the oblique-varying period, the modulated gate control signal firstly changes to a predetermined voltage in a first slope, and then changes in a second slope until the vertical-varying period. In the vertical-varying period, the modulated gate control signal changes vertically or nearly vertically.

Gate output control method and corresponding gate pulse modulator

A power transmission circuit, a light source module including the power transmission circuit, and a panel display device are provided. The power transmission circuit includes a substrate, a power transmission layer, a metal shielding layer, a first protective layer, and a second protective layer. The substrate has a first surface and a second surface with the power transmission layer and the metal shielding layer respectively formed thereon. The metal shielding layer covers a projection region of a transmission section of the power transmission layer. The first and second protective layers are respectively disposed on the power transmission layer and the metal shielding layer and opposite to the substrate to protect the power transmission layer and the metal shielding layer.

Power transmission circuit with EMI shielding, lighting module, and panel display module

The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.

High surface dopant concentration semiconductor device and method of fabricating

The present invention relates to a gate pulse modulation (GPM) circuit and the application of same in a liquid crystal display for improving the display performance thereof. The gate pulse modulation circuit is configured to modulate multi-phase clock pulse signals so as to correspondingly generate odd gate pulse waveforms and even gate pulse waveforms that are different from one another.

Gate pulse modulation circuit and liquid crystal display thereof

Growing community of inventors

Hsinchu, Taiwan

Tsung-Hung Lee