United Microelectronics Corp.

Tsung-Hsun Wu

Shih-Hao Liang

Chi-Mao Hsu

Tsuo-Wen Lu

Po-Jen Chuang

Shih-Cheng Chen

Li-Hsuan Ho

Shu-Wei Yeh

Chih-Ming Su

Sheng-Yuan Hsueh

Kuo-Hsing Lee

Kun-Hsien Lee

Chang-Chien Wong

Zhi-Xian Chou

Po-Lin Chen

Liang-Wei Chiu

Yu-Tse Kuo

Shih-Chieh Hsu

Chi-Horn Pai

Ching-Hsiang Tseng

Pin Tsao

Ming-Siou Wu

Yen-Yu Shen

Ming-Hsiu Wu

Chien-Hui Huang

A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Semiconductor device having contact plug connected to gate structure on PMOS region

A random access memory, including a write transistor with a gate electrically connected to a write word line and a drain electrically connected to a write bit line, a first read transistor and a second read transistor with gates electrically connected to a source of the write transistor to form a storage node, drains electrically connected to a read bit line and a common source electrically connected to a read word line so that the first read transistor and a second read transistor are in parallel connection, and a capacitor electrically connected to the storage node.

Random access memory with metal bridges connecting adjacent read transistors

A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.

Static random access memory (SRAM) and method for fabricating the same

The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Semiconductor memory cell and the forming method thereof

A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.

One-time programmable memory device

A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

SRAM structure

The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least two inverters coupled to each other for storing data, each inverter comprising an L-shaped gate structure on a substrate, the L-shaped gate structure includes a first portion arranged along a first direction and a second portion aligned along a second direction, wherein the first portion crosses a first diffusion region to form a pull-up device, and the first portion crosses a second diffusion region and a third diffusion region to form a pull-down device, and each of the inverters includes a local interconnection layer, crossing the second diffusion region and the third diffusion region.

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

The present invention provides a memory cell. The memory cell includes a static random access memory (SRAM) cell located on a substrate. The SRAM cell includes a first storage node. At least one tunneling field-effect transistor (TFET), the gate of the tunneling field-effect transistor is electrically connected to the first storage node of the SRAM cell. A read bit line (RBL) electrically connected the drain of the TFET. A read terminal which is connected to a read port voltage (Vrp) and electrically connects to a source of the TFET.

Static random access memory cell, layout pattern and operation method thereof

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

Growing community of inventors

Kaohsiung, Taiwan

Tsung-Hsun Wu