Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsung-Hsueh Yang

Shih-Chang Liu

Chung-Chiang Min

Chang-Ming Wu

Yao-Wen Chang

Yuan-Tai Tseng

Hung Cho Wang

Sheng-Huang Huang

Chia-Hua Lin

Harry-Hak-Lay Chuang

Fu-Ting Sung

Chang-Chih Huang

Chia-Shiung Tsai

Kuo-Chyuan Tzeng

Sheng-Chieh Chen

Yi-Jen Tsai

A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.

Encapsulated phase change material switch and methods for forming the same

A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell may be manufactured by a method comprising forming a multi-layer stack and patterning the same to form the hard mask layer, the top electrode layer and the switching dielectric layer to form a hard mask, a top electrode and a switching dielectric. A sidewall spacer is formed alongside the hard mask, the top electrode, and the switching dielectric with a material different than the hard mask. The bottom electrode layer is patterned according to the sidewall spacer to form a bottom electrode. A dielectric layer is formed surrounding the bottom electrode, the sidewall spacer and overlying the hard mask. An etch is performed followed by a conductive material filling to form a top electrode via extending through the dielectric layer and the hard mask to reach on the top electrode.

Memory device having via landing protection

An embodiment phase-change memory device includes a first electrode formed over an interconnect layer, a phase-change memory element formed over the first electrode, a second electrode formed over the phase-change memory element, and an oxygen-free spacer layer formed over sidewalls of the phase-change memory element. The phase-change memory element may include a germanium-antimony-tellurium alloy or an aluminum-antimony alloy. The phase-change memory device may include a carbon layer, configured as a heater element, formed between the first electrode and the phase-change memory element. The oxygen-free spacer layer may include SiN, SiC, or SiCN and may further include chlorine, fluorine, argon, chlorine and argon, fluorine and argon, or a mixture of chlorine, fluorine, and argon. The oxygen-free spacer layer may further include a composition that varies with position within the oxygen-free spacer layer. A further embodiment includes the phase-change memory device coupled to a selector element within a phase-change random-access memory structure.

In-situ formation of a spacer layer for protecting sidewalls of a phase change memory element and methods for forming the same

Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.

Sidewall spacer structure for memory cell

Semiconductor devices and methods of manufacturing the semiconductor devices are provided in which spacers are utilized in order to help protect bottom electrode vias. In embodiments, an opening is formed through dielectric layers, and spacers are formed along sidewalls of the dielectric layers. A bottom electrode via is formed adjacent to the spacers, a bottom electrode is formed, a magnetic tunnel junction (MTJ) structure is formed over the bottom electrode, and a top electrode is formed over the MTJ structure. The structure is patterned, and the spacers help to protect the bottom electrode via from undesired damage during the patterning process.

Semiconductor devices and methods of manufacturing

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.

Semiconductor devices and methods of manufacturing the semiconductor devices are provided in which spacers are utilized in order to help protect bottom electrode vias. In embodiments, an opening is formed through dielectric layers, and spacers are formed along sidewalls of the dielectric layers. A bottom electrode via is formed adjacent to the spacers, a bottom, electrode is formed, a magnetic tunnel junction (MTJ) structure is formed over the bottom electrode, and a top electrode is formed over the MTJ structure. The structure is patterned, and the spacers help to protect the bottom electrode via from undesired damage during the patterning process.

A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.

Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench.

Method of manufacturing capacitor structure

The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.

Top electrode cap structure for embedded memory

A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates

A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.

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Taichung, Taiwan

Tsung-Hsueh Yang