Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsung-Hsiung Li

Chewn-Pu Jou

Kuang-Kai Yen

Fu-Lung Hsueh

Hsieh-Hung Hsieh

Yi-Hsuan Liu

Huan-Neng Chen

Feng Wei Kuo

Hung-Chih Lin

Mill-Jer Wang

Hao Chen

Ching-Nen Peng

Wei-Li Chen

Fan-ming Kuo

Ming-Chieh Liu

Shi-Hung Wang

Kuang Kai Yen

Jiunn-Der Yu

A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.

Method and apparatus for RFID tag testing

A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure.

Three-dimensional integrated circuit and method for wireless information access thereof

A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block.

Built-in self repair for memory

A voltage scaling circuit includes a first critical path and an edge detection unit. The first critical path includes an input and an output. The edge detection unit includes a first input, a second input, a counter and a time-to-digital converter (TDC). The input of the first critical path is electrically connected to the first input of the edge detection unit, and the output of the critical path is electrically connected to the second input of the edge detection unit. The counter is configured to measure a duration between an active edge of a start signal on the first input of the edge detection unit and an active edge of a stop signal on the second input of the edge detection unit in a clock period basis. The TDC is configured to measure a beginning portion and an end portion of the duration.

Method and apparatus of voltage scaling techniques

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Taipei, Taiwan

Tsung-Hsiung Li