Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Wistron Neweb Corporation

Ambarella International LP

Ambarella, Inc.

Tsung-Han Wu

Tong-Min Weng

Chih-Wei Chang

Cheng-Ta Wu

Ting-Chun Wang

Ke-Ying Su

Hsien-Hsin Sean Lee

Lun-Kuang Tan

Wei-Ming You

Cheng-Han Yang

Pei-Chien Yu

Liang-Yu Yen

Chih-Chun Lee

Hsin-mei Lin

Wei-Kang Che

I-Chun Hsieh

Hsi-Yen Chang

Yu-Ting Hsiao

Chung-Hsing Wang

Che-Li Lin

Jen-Pan Wang

Ming-Luen Liou

Siu-Chuang Ivan Lu

Chih-Cheng Chou

Chia-Ming Ho

Chi-Yao Yu

Yu-Shuo Wu

Hsien-Sheng Huang

George Chien

Yu-Hong Pan

Chun-Yi Huang

Chih-Hsuan Hsieh

Ching-Gu Pan

Hua-Shan Chou

Huan-Kuan Su

Seng-Chong Tiun

Yu Ding

Kun-Ting Tsai

Po-Ching Lee

Shu-Ching Tsai

A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

Method for forming semiconductor device and resulting device

An electronic device is provided. The electronic device includes a housing having an insertion slot, a connecting interface, and an adaptor card. The connecting interface is disposed in the housing for connecting with a first electronic module or a second electronic module separately and has a first connecting part and a second connecting part. The adaptor card is detachably disposed in the housing and includes a flow guide. When the electronic device is in a first mode, the first electronic module is connected to the first connecting part, and the adaptor card is disposed between the insertion slot and the connecting interface. The flow guide directs an airflow toward the first electronic module. When the electronic device is in a second mode, the adaptor card is removed from the housing, and the second electronic module is connected to the first connecting part and the second connecting part.

Electronic device and adaptor card thereof

A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.

Anti-reflective coating by ion implantation for lithography patterning

An apparatus includes a plurality of cameras and a circuit. The cameras may be mounted on a vehicle and configured to generate a plurality of initial video signals of a scene outside of the vehicle. A plurality of fields of view of adjoining ones of the cameras may spatially overlap each other. The circuit may be configured to (i) store calibration values of the cameras generated during a calibration process, (ii) modify at least one of the initial video signals by applying the calibration values and (iii) generate a final video signal suitable to display to a user of the vehicle by stitching together the initial video signals. The calibration values may be used by the circuit to generate approximately continuous brightness within the scene in the final video signal.

Color and brightness calibration for video stitching

Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.

Methods of fabricating Fin Field Effect Transistor (FinFET) devices with uniform tension using implantations on top and sidewall of Fin

A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.

A method for forming a semiconductor device includes steps of: forming at least one gate structure comprising a gate electrode over a substrate, and forming a first dielectric layer of a first dielectric material along a side wall of the at least one gate structure. The first dielectric layer of the first dielectric material includes fluorine doped silicon oxycarbonitride with a doping concentration of fluorine. The dielectric constant of the first dielectric layer is adjusted through the doping concentration of fluorine.

A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.

Device including resistor-capacitor (RC) structure and method of making the same

A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

FinFET

A system using a USB Type-C interface is provided. This system not only transmits the normal USB signal but also supports a DisplayPort Alternate Mode. Moreover, due to the novel pin arrangement of the multi-function control circuit, the cost of the overall system is reduced, and the area of the printed circuit board is effectively reduced.

System and circuit using USB Type-C interface

A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.

Method of forming gate and finFET

A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.

Method and apparatus for capacitance extraction

A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Multi-patterning mask decomposition method and system

Growing community of inventors

Hsinchu, Taiwan

Tsung-Han Wu