Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsung-Chieh Tsai

Juing-Yi Wu

Liang-Yao Lee

Jyh-Kang Ting

Tung-Heng Hsieh

Chun-Yi Lee

Ru-Gun Liu

Hui-Zhong Zhuang

Sheng-Hsiung Wang

Yung-Che Albert Shih

Jih-Churng Twu

Chia-Chun Cheng

Yu-Cheng Yeh

Jhy-Kang Ting

Bao-Ru Young

Ming-Hsi Yeh

Ming-Dar Guo

Chin-An Chen

Pei-Tzu Wu

Chung-Te Lin

Harry-Hak-Lay Chuang

Li-Chun Tien

Kong-Beng Thei

Ting-Wei Chiang

Chien-Chih Chou

Yi-Huan Chen

Kuei Shun Chen

Yu-Chang Jong

Cheng-Yi Huang

Wei-Ming You

Ta-Wei Lin

Yen-Sen Wang

George Liu

Szu-Hsien Liu

Jhe-Ching Lu

Jhu-Min Song

Chin-Hsiung Ho

Fu-Hsiung Yang

Huan-Chih Yuan

Li-Hsuan Yeh

Rong-Hui Kao

Kuo-Hung Liao

Cheng Cheng Kuo

Yu-Lun Lu

Ming Te More

Yuhi-Jier Mii

Roung-Hui Kao

Sheng-Hsiung Tseng

Yao-Pin Huang

Ching-Hsun Hsu

Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.

Checkerboard dummy design for epitaxial open ratio

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first contact and a second contact disposed over a substrate. A center of a first upper surface of the first contact is laterally separated from a center of a second upper surface of the second contact by a first distance. A first interconnect contacts the first upper surface and a second interconnect contacts the second upper surface. A center of a first lower surface of the first interconnect is laterally separated from a center of a second lower surface of the second interconnect by a second distance that is greater than the first distance.

Different scaling ratio in FEOL / MOL/ BEOL

A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.

Semiconductor structure and method for manufacturing thereof

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.

Gate-all-around device with different channel semiconductor materials and method of forming the same

A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Cell layout and structure

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.

A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

Conductive line patterning

In a method for manufacturing a semiconductor device, a first dielectric layer is formed over an underlying structure disposed on a substrate. A planarization resistance layer is formed over the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the planarization resistance layer. A planarization operation is performed on the second dielectric layer, the planarization resistance layer and the first dielectric layer. The planarization resistance film is made of a material different from the first dielectric layer.

Semiconductor device and manufacturing method thereof

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.

Different scaling ratio in FEOL/ MOL/ BEOL

A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.

Mask optimization for multi-layer contacts

A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment.

Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device

A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner. Accordingly, the second distance generally prevents the rounded corner of the exposure region from overlapping the active device region.

Method for preventing photoresist corner rounding effects

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Chu-Bei, Taiwan

Tsung-Chieh Tsai