Vanguard International Semiconductor Corporation

First International Computer, Inc.

Other

Picta Technology Inc.

Tsung-Chieh Chen

Yi-Liang Peng

Kuang-Ho Liao

Ken-Hsiung Hsu

Chun-Liang Chen

Cheng-Chieh Hsu

Chuen-Jye Lin

The provision of a semiconductor wafer, which has been formed with a plurality of chips that each can be existent independently; the pre-cure process, in which the buffer layer has not been completely baked or hardened yet, but just for making the buffer layer be in stable condition; the pre-cut process, in which a cut is made at the position of the buffer layer corresponding to the boundary of each IC to make a gap exited between each two adjacent ICs without containing any buffer layer; the post-cut process, in which the buffer layer has completely baked and hardened; the singulation process, in which the both wafer and buffer layer are cut simultaneously to make the plural ICs separated from each other to become IC device that can act independently. Since the invention has processed pre-cut before the complete hardening, so when processing the complete bake, because there is pre-remaining space available for the buffer layer for thermal expansion, it can reduce the stress applied on the wafer to further keep the completeness of the wafer.

Packaging process for wafer level IC device

A method for forming a back-to-back dual-chip package and package formed are disclosed. In the method, a first IC chip is bonded in its inactive surface to an inactive surface of a second IC chip, while solder balls planted on the active surfaces of both chips. One of the chips is connected to lead fingers of a lead frame by the solder balls. The dual-chip assembly together with the lead fingers are then encapsulated in an insulating material for protecting the chips while exposing substantially the solder balls on the IC chip that was not connected to the lead fingers. The encapsulated assembly can then be connected to an outside circuit, such as a printed circuit board, by forming the exposed finger leads for soldering and by fusing the solder balls to the outside circuit. The present invention novel method and device formed advantageously utilize existing chip design for achieving a high density device at a low cost. For instance, by doubling up two memory chips and doubling its memory capacity, existing memory chip design and existing fabrication equipment can be utilized to avoid the high costs of a new high capacity chip design and a new fabrication equipment. The present invention method further presents the benefit that a high density device is achieved with substantially no additional use of chip real estate.

Method for fabricating a dual-chip package and package formed

A method for forming chip scale packages and devices formed by utilizing a wire bonding technique and an interposer board which has recessed peripheral regions are disclosed. In the method, an IC die is bonded on its active surface to an interposer which is constructed with a recessed peripheral regions equipped with interconnections such that shorter bond wires may be run between the IC die and the interposer. The interposer is further equipped, in a top planar surface, with a plurality of interconnections for the subsequently forming of solder balls for connecting to an outside circuit such as a printed circuit board. The present invention novel method further provides the benefit that the shorter wire bonds formed alleviate the wire sweep problem normally occurs in the plastic encapsulation process for such a package.

Method for wire bonding a chip to a substrate with recessed bond pads and devices formed

A dual-sided heat dissipating structure for BGA package includes a step-shaped first heat dissipating member adhering to an active side of the chip and a dish-shaped perforated second heat dissipating member adhering to a non-active side of the chip so that heat generated in the chip may be dissipated more effectively. The step surface first heat dissipating member may also serve as a press mold to enable bonding of inner leads of the substrate to the bonding pads of the chip be done along with adhering of the first heat dissipating member to the chip at same process in the mean time without additional process or equipment. The perforated second heat dissipating member enables moisture escaping from the package to avoid pop corn effect resulting from IR Reflow test. The package may be made at a thin thickness and low cost.

Dual-sided heat dissipating structure for integrated circuit package

An enhanced heat dissipating Chip Scale Package (CSP) method and devices include preparing a heat dissipating base with a recess surrounded by a guarding wall. A chip with an integrated circuit (IC) layout is adhered the heat dissipating base in the recess. A substrate with a metallic circuit layer that is smaller size than the chip is then adhered to the chip. Then coupling the metallic circuit layer with the IC layout. A non-conductive resin is then filled in the recess within the guarding wall and covers the coupling portion. The resulting package device produced by means of BGA package process is small size and has enhanced heat dissipating property. The Package size/chip size ratio may be lower than 1.2 to meet the CSP requirements.

Enhanced heat dissipating chip scale package method and devices

A thin enhanced TAB BGA package includes an IC chip, a substrate having a center opening and one side laid with a metallic circuitry which has a plurality of inner leads extending to the center opening, a plurality of metallic solder balls attached to the substrate at one side and coupling with the metallic circuitry, and a heat dissipating member adhering partly to the a side of the chip and partly to the substrate for heat dissipating, positioning and supporting the IC chip and the substrate. The IC chip has a another side exposed to ambience to add heat dissipating effect. The heat dissipating member has about same thickness as the substrate. Hence the ball grid array package may be made of a small size and thin thickness. The adhering of heat dissipating member to the chip and substrate may be done at the same process of bonding the inner leads to the IC chip. Thus the thin enhanced TAB BGA package of this invention may be produced at low cost without additional equipment or process.

Thin enhanced TAB BGA package having improved heat dissipation

A multi-chips semiconductor package and fabrication method mainly combines LOC and BGA techniques to overlap one chip upon another chip in an IC component package. One chip uses leads of a lead frame as connection interface of the circuit in the chip to outside. Another chip uses solder balls as connection interface of the circuit in another chip to outside. The two chips are supported by the lead frame without a substrate used in a conventional BGA package. The two chips may have same or different function. The structure is simple and easy to produce at low cost. The size and length of the IC component is smaller than the one produced by conventional multi-chips packaging techniques.

Multi-chips semiconductor package and fabrication method

A lead frame equipped with modified lead fingers which have inclined tip portions for achieving an improved wire bond is provided. The inclined tip portions on the lead fingers can be formed in a stamping process with an angle on a top surface of the inclined tip portion measured at smaller than 30.degree. from a horizontal plane of the lead finger. It is preferred that the inclined angle should be between about 5.degree. and about 30.degree., and more preferred that the angle should be between about 5.degree. and about 20.degree.. A wedge bond formed on the inclined tip portion of a lead finger has improved thickness and thermal stress endurance. The thermal stress endurance may be improved by at least 20% and preferably by at least 50% when tested in a thermal cycling test between 150.degree. C. and -65.degree. C.

Growing community of inventors

Taipei, Taiwan

Tsung-Chieh Chen