Micron Technology Incorporated

Other

Tsung Che Tsai

Ko Han Lin

Keizo Kawakita

Shigeru Sugioka

Raj K Bansal

Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

Bump coplanarity for semiconductor device assembly and methods of manufacturing the same

Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.

Apparatuses and methods including patterns in scribe regions of semiconductor devices

A magnetic energy reinforcing device including a base having an axial through hole and a plurality of chambers symmetrically spaced around said through hole, a plurality of magnets respectively mounted in each chamber on the base, and a plurality of antimagnetic plates mounted on the base and respectively disposed adjacent to the magnets at an outer side to concentrate the magnetic energy of the magnets into the axial through hole.

Growing community of inventors

Tainan, Taiwan

Tsung Che Tsai