Dynalogic

Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Siemens Components, Inc.

Dynachip Corporation

Gloval Unichip Corp.

Tsung C Whang

Suresh M Menon

Paul T Sasaki

Yi-Chieh Wang

Stanley Wilson

Michael Franz

A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof

The present invention discloses an efficient way to connect multiple integrated circuit dies using redistribution layers (RDL) for making wire connections. Antenna diodes are used to create ground paths so as to remove non-sticking pads on the RDL to ensure the integrity of the wire connections before packaging the multiple integrated circuit dies into a system-in-package (SIP) chip, thereby eliminating unnecessary yield loss in a functional test caused by the non-sticking pads. In another aspect, electrostatic discharge (ESD) protection can be provided through the antenna diodes across two different power domains by disposing a diode in one integrated circuit die for ESD protection of a terminal in another integrated circuit die.

Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. The PLD uses BiCMOS circuit elements to make use of the speed advantages of bipolar technology while also enjoying the limited power consumption of CMOS technology.

High speed programmable logic architecture

Programmable logic cell with input polarity control

A biasing system for a differential amplifier includes an NMOS current source and a gate bias voltage generator. The gate bias voltage generator produces a bias voltage VNCS to control the NMOS current source. The gate bias generator includes a reference current generator to produce a reference current relatively independent of supply voltage variations. A temperature compensator regulates the reference current to provide a temperature compensated current. A current mirror duplicates the temperature compensated current to a bias voltage generator. The bias voltage generator generates the bias voltage.

Programmable logic bias driver

A programmable logic device includes a plurality of logic cells in which logic functions are performed, a plurality of input lines for supplying signals to be processed by the logic cells, a plurality of output lines for receiving signals that have been processed by the logic cells, and a plurality of repeater circuits combining bipolar and CMOS transistor technologies for transferring data from one point in the PLD to another point. Unidirectional repeater circuits transfer data from a first data bus in the PLD to a second data bus in the PLD. Bidirectional repeater circuits maintain signal integrity by transferring data along the length of a single PLD data bus. The bipolar technology in the repeater circuits provides superior speed in data transfer, while the CMOS technology limits power consumption of the repeater circuits.

BICMOS repeater circuit for a programmable logic device

A circuit technique is presented for mixing current mode logic and emitter coupled logic in a manner which reduces active and passive component counts for performing recognized logic functions. The reduced counts permit greater circuit density while reducing power consumption in comparison to conventional emitter coupled logic circuitry. The mixing is also provided in a way for making all imputs and outputs compatible with conventional emitter coupled logic levels. Various logic circuits are illustrated to demonstrate the versatility of the technique. For example, a transparent high D-latch (FIG. 2), a D flip-flop with true output (FIG. 4), a two-to-one multiplex latch (FIG. 6), and other D flip-flops having set and reset inputs (FIG. 7), multiplex data inputs (FIG. 8), and Exclusive OR data inputs (FIG. 9) are circuits wherein the inventive technique is employed to advantage.

Growing community of inventors

Cupertino, CA, United States of America

Tsung C Whang