Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Tsuneyuki Suzuki

Tetsuya Tanaka

Takeshi Tanaka

Tokuzo Kiyohara

Taketo Heishi

Masaki Maeda

Hideshi Nishida

Hajime Ogawa

Hazuki Okabayashi

Nobuo Higaki

Akihiro Furuta

A processor according to the present invention includes a decoding unit, an operation unitand others. When the decoding unitdecodes Instruction vcchk, the operation unitand the like judges whether vector condition flags VC&#x2dc;VC() of a condition flag register (CFR)are all zero or not, and (i) sets condition flags Cand Cof the condition flag register (CFR)to 1 and 0, respectively, when all of the vector condition flags VC&#x2dc;VCare zero, and (ii) sets the condition flags Cand Cto 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC&#x2dc;VCare stored in the condition flags C&#x2dc;C

Processor executing SIMD instructions

The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers

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Takatsuki, Japan

Tsuneyuki Suzuki