Fujitsu Corporation

Tsuneo Nakata

Ryosuke Oishi

Koichiro Takayama

Hiroaki Iwashita

Akio Matsuda

Qiang Zhu

Hirokazu Anai

Hitoshi Yanami

Rafael Kazumiti Morizawa

Jawahar Jain

Stergios Stergiou

Yuzi Kanazawa

Shinya Kuwamura

Hidenao Iwane

Fumiyasu Hirose

Takashi Hasegawa

Takahide Yoshikawa

Satoshi Kowatari

In particular embodiments, a method includes analyzing a binary decision diagram (BDD) representing a data stream from a sensor to determine a compression rate of the BDD and indicating a sensor malfunction in the sensor if the compression rate of the BDD deviates from a specified compression rate range.

Detecting sensor malfunctions using compression analysis of binary decision diagrams

A design support apparatus for determining a plurality of objective functions for modeling an object having a plurality of elements, each of the elements providing variable geometrical parameters, the design support apparatus includes a memory for storing the variable geometrical parameters and a processor for executing a process including: determining boundary information associated with specified geometrical parameters of the elements which indicate a state of contact between the elements, dividing the variable geometrical parameters into a plurality of groups on the basis of the boundary information, and determining the plurality of objective functions for each of the groups by using the variable geometrical parameters.

Support apparatus using objective function

An objective function can be mathematically approximated using a prescribed number of sample sets of design parameters and sets of a plurality of objective functions computed corresponding to them. A logical expression indicating a relation between or among arbitrary two or three objective functions of the plurality of mathematically approximated objective functions is computed as an inter-objective-function logical expression and a region that the arbitrary objective function values can take is displayed as a feasible region in an objective space corresponding to the arbitrary objective functions. Furthermore, a point or area in a design space corresponding to arbitrary design parameters corresponding to a point or area specified by a user in the displayed feasible region is displayed.

Multi-objective optimal design support device, method and program storage medium

A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Verification supporting system

Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.

Verification of requirements specification, design specification, and computer-readable storage medium apparatus, and method thereof

In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Verification supporting apparatus, verification supporting method, and computer product

A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

Circuit design data conversion apparatus, circuit design data conversion method, and computer product

An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.

Method and apparatus for verifying specification, and computer product

A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.

Program, apparatus and method for verifying program

A verification aiding apparatus includes an acquiring unit that acquires implementation description information of a verification target circuit, and a classifying unit that classifies registers in the verification target circuit for each type of processing for each command executable by the verification target circuit. Thus, implementation description classification information can be obtained. A setting unit performs a verification priority setting process and a generating unit performs a sequential command generating process, and a sequential command is output.

Method and apparatus for aiding verification of circuit, and computer product

An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link generating unit generates, based on the association information, a link that couples nodes generated by the node generating unit. A sub-chart generating unit configured to generate a plurality of sub-charts by dividing a chart indicating a content of the specification description, based on the node and the link. A function-module generating unit generates, for each of the sub-charts, a function module that executes a function based on the processing information corresponding to the node in the sub-chart and the association information corresponding to the link in the sub-chart.

Design support apparatus, design support method, and computer product for designing function module from specification description

A verification apparatus which verifies whether or not a finite state machine indicating the operation of a synchronous sequential machine satisfies the property indicating the functional specification repeats the image computation in the M and the computation of a set product by q starting with the state set p when the finite state machine M, the subset q of the state of the M, and the subset p of the q are given; and checks the relation of the state set of the computation process. As a result, it can be determined, starting with a certain state in the p, whether or not a state transition path which eternally does not exceed the q exists.

Logical device verification method and apparatus

First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.

Automatic instruction string generation method and device for verifying

A method for generating a test pattern for use with a scan circuit utilized in detecting a degenerative failure in a synchronous sequential circuit including a memory element unit, having a scan register, and a combination circuit unit for receiving an external input and inputting a value from the memory element unit, and for supplying an external output and outputting a value to the memory element unit. The method includes generating, for an undetected failure, a test pattern for use in a combinational circuit. The method also includes generating a test pattern series for detecting a different failure by observing its external output value and by changing the external input value with the value set in a scan register of the memory element unit.

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Kawasaki, Japan

Tsuneo Nakata