Nec Corporation

Other

Nec Electronics Corporation

Tsuneo Koike

Hideaki Suzuki

Kazuo Ando

Akihisa Saitou

To advance a read response in a split transaction bus system. An access time prediction circuit measures an elapsed time from a time when a read command is issued, and outputs a parking indication PI to a slave device to be read during the last clock cycle before a predicted access time Tac elapses. When receiving the parking indication PI, an arbiter parks the slave device to be read by transmitting a bus grant thereto under the control of a parking control unit unless a bus is being used, and places the parked slave device to be read at the highest priority.

Split transaction bus system

A method for stabilizing material physical properties of recyclable bumpers including the steps of: separating coating from raw material obtained by cleaning, fracturing and drying recyclable bumpers to form a recycled matrix; mixing an additive with the recycled matrix; melting and extruding the mixed matrix with an extrusion machine; cutting the molten and extruded matrix to produce pellets; introducing the pellets into a tank of a predetermined capacity; and mixing the pellets in the tank for a predetermined period of time while again delivering the pellets in the tank to an introduction opening of the tank for reintroduction into the tank in parallel with the pellets that are to be newly introduced.

Method and apparatus for stabilizing material physical properties of recyclable bumpers

The invention provides a semiconductor device in the form of an LSI circuit having a large number of terminals wherein an increase of the number of pad terminals for a power source potential and wherein a ground potential does not increase the inductances of wiring lines to the pad terminals and the terminals are arranged efficiently. The semiconductor device includes a semiconductor chip having a semiconductor substrate on which a first pad arrangement region, a buffer arrangement region and a second pad arrangement region are successively assured in this order toward the outer side around an internal circuit formation region and arranged in parallel to each other. A first power source pad and a first grounding pad for an internal circuit are provided in the first pad arrangement region while a plurality of pads for inputting and/or outputting signals are provided in the second pad region. The pads are bonding connected by respective thin metal lines to external lead terminals provided on a support.

Semiconductor device

A static random access memory device is equipped with a reset controller capable of performing a reset operation at high speed and with a reduced circuit configuration. The device has a memory cell including first and second data holding nodes and selectively connected to an associated bit line. The memory cell is equipped with a logic device for supplying a first voltage in common to the first and second holding nodes and, in response to a reset mode signal, supplying the first voltage to the first holding node and a second voltage being different from the first voltage to the second holding node. In this reset operation, a word decoder and word driver circuit is deactivated and inhibited from selecting and driving any word line.

Static random access memory device having reset controller

A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for supplying data to the external memory and receiving data from the external memory, and a control logic for controlling data exchange between the CPU and the external memory with a predetermined unit amount of data processing of the central processing unit. The external memory includes first and second DRAMs and the CPU executes the data exchange with units of four words. Each DRAMs has a memory area divided into a number of sub-areas each have four continuous addresses, so that the sub-areas of the first DRAM and the sub-area of the second DRAM are alternately assigned in continuous addresses in one memory space formed of the first and second DRAMs. When an continuous addresses are supplied, a controller controls so that the first and second DRAMs are alternately accessed.

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Tokyo, Japan

Tsuneo Koike