Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Tokyo Shibaura Electric Co., Ltd.

Tsuneo Kinoshita

Kazuyuki Sato

Isamu Yamazaki

Fumitaka Sato

Ryusuke Soneoka

A one-chip IC, having a function module for converting bus widths at least between 32 and 16 bits and between 32 and 8 bits and peripheral control function modules connected to an internal bus through the bus width-conversion function module, is arranged between various peripheral devices and a 32-bit microprocessor compatible with existing 16-bit personal computer software, thereby realizing a personal computer.

32-bit personal computer using a bus width converter and a latch for

A multiple data processing system includes first and second microprocessors for executing the same data processing in parallel fashion. A selector selectively delivers one of the output data of the microprocessors to an external I/O device. A comparator detects an off normal data processing state by comparing the output data of the first microprocessor with the output data of the second microprocessor. An operation monitor evaluates the operation state of the microprocessors in response to a signal from the comparator and instructs the selector to deliver output data sent from a normal channel to the external I/O device.

Multiple data processing system with a diagnostic function

According to an large scale integration (LSI) system, different types of macrocells which are required to establish a predetermined system and which have a first-layer of wiring and a glue circuit for compensating for the functions not provided by the marcrocells alone, are formed on a single semiconductor substrate. The different types of macrocells correspond to different types of independent LSIs constituting the predetermined system. The macrocells have the same main circuits as those of the independent LSIs. The pattern configuration of the main circuits of the macrocells adopts the patterns of the corresponding independent LSIs. A second-layer of wiring is connected between the macrocells and between the macrocells and the glue circuit as needed.

Monolithic semi-custom LSI

In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address. The output signal of the comparator is stored in a memory section which is provided to correspond to the prefetched instruction buffer, and when an instruction stored in the prefetched instruction buffer is transferred to an instruction register, the signal stored in the corresponding memory section is also read out and used to determine whether to stop execution. Further, whenever access is made to main memory a signal indicating whether the access is legal is externally generated and may be stored in a second memory section. Like the address matching signal, this signal is read out when the corresponding instruction from the prefeteched instruction buffer is transferred to the instruction register. An illegal address interruption is produced when this signal indicates that the address was illegal.

Information-processing system having a single chip arithmetic control

A logic circuit on a substrate is switchable between a test mode and an operational mode. First and second NOR gates are cross-coupled and may be switched between an operational mode and a test mode by the application of a control signal to first and second transfer gates coupled to the inputs of the NOR gates. The first NOR gate includes a p-type region and an n-type region formed in said substrate and traversed with first and second conductive layers insulated from the p and n-type regions. Thus, the first NOR gate includes two p-channel transistors and two n-channel transistors. The second NOR gate is also formed by a p-type region and an n-type region traversed with third and fourth conductive layers. Thus, the second NOR gate also includes two p-channel transistors and two n-channel transistors. The transfer gates are located on the substrate between the first and second NOR gates. Both transfer gates include an n-type region formed in the substrate with a conductive layer disposed over the n-type region. In the operational mode, the cross-coupled NOR gates may perform as a flip-flop. In the test mode, each NOR gate essentially becomes an inverter.

Logic circuit testable as an inverter pair and operable as a flip-flop

A 16-bit microprocessor (.mu.P) system uses memory access data consisting of: a status field for memory control data including a specific bit; a segment field; and a 16-bit address field. In a .mu.P, an instruction under execution comprises an .alpha. instruction in an operand fetch cycle, an index-modified value of a 16-bit lower logical address is set in an MAR, and a sum of an 8-bit upper logical address word and a carry flag is set in an SGB (Segment Register B). The .mu.P sets the memory control data having the specific bit of a first logic level in an MCS (Memory Control Status Register), and thereafter generates the memory access data. In this case, the content of the SGB is used for the segment field in place of the segment number stored in an SGA (Segment Register A). When the specific bit of the status field of the memory access data from the .mu.P, is set at a second logic level, a segment/page table is accessed by the segment field and part (page number) of the address field, thereby generating the page data. A basic address space is accessed by a physical address obtained by linking the page data and the remaining data (displacement) of the address field. On the other hand, when the specific bit is set at the first logic value, a expanded address space is accessed by a physical address obtained by linking the segment field and the address field.

16-bit microprocessor system

A semiconductor device has an array section formed on a semiconductor chip. A memory section is also formed on the chip together with the array section. The memory section has a decoder for producing an address signal, memory blocks whose locations are commonly designated by the same address signal from the decoder, a selector controlling circuit for generating a control data designating at least one of the memory blocks, and a selector for selecting the designated block and for passing the input/output data to and from the selected block in accordance with the control data from the selector controlling circuit.

Semiconductor device

A gate array is used as the base component of a custom-circuit LSI. A number of logic cells are arranged in the form of a matrix in the first area of the gate array. These logic cells are interconnected by a metal pattern or patterns to build a custom-circuit. Driver cells for energizing the output and input signals of the custom-circuit are formed in the second area of the gate array. Bonding pads, which will be used as the input/output terminals of the custom-circuit, are formed in the third area of the gate array.

Method for manufacturing a custom-circuit LSI, and a gate array device

A logic circuit is formed on a gate array chip together with a custom-circuit. Bonding pads mounted on the gate array chip are used as the terminals which send forth or receive data and control signals. The logic circuit is provided with a shift register for holding data to test the flip-flops of the custom-circuit and output data from the flip-flops. The shift register comprises the stages each of which holds 1-bit data selected by a read control signal. The output terminals of the stages are respectively connected to the input terminals of the flip-flops of the custom-circuit through the AND gates which are rendered conducting in response to a set control signal. The output terminals of the flip-flops are connected to the input terminals of the respective stages of the shift register.

Transfer circuit for defect inspection of an integrated circuit

In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits. An interruption signal from an I/O device and a signal indicating an abnormal condition of a power source, for example, may be input to the arithmetic control unit from external devices on the common bus as part of a group of external signals occupying only a portion of the common bus simultaneously with the fetching of a microinstruction on the remaining portion of the common bus. When exchanging a plurality of kinds of data with different phases between the arithmetic control unit and external devices on the common bus, an external status signal unique to each phase is input to the arithmetic control unit on a common signal line in synchronism with each phase.

Information processing system including a one-chip arithmetic control

A tester for an electronic engine control system is provided with an output circuit through which test signals are delivered to the electronic engine control system. The electronic engine control system responds to the test signals to deliver response signals to the tester. The response signals outputted are sent through an input circuit to a judgement circuit where the response signals are operated upon, compared and judged to check to see whether operation of the engine control system is proper or not. The result of the checking is displayed by a display circuit.

Tester for electronic engine control systems

A microprogram controlled system to which is applied the vertical type microprogramming technique. Microinstructions fetched from a control stage are decoded in a control decoder, which controls gates of registers in a central processor to execute the microinstructions. The microinstructions include an extension field in the format to modify the functions thereof.

Microprogram controlled system

A minicomputer system comprising an arithmetic control unit integrated on a one-chip semiconductor device using n-channel silicon gate E/D MOS technology and a control storage separate from and connected to the arithmetic control unit for storing microinstructions. The arithmetic control unit includes two kinds of read only memories, each having a small memory capacity. The first read only memory stores start addresses of specific microinstructions for phase control, an illegal instruction trap and an initialization trap. The second read only memory stores auxiliary microinstructions to handle operations involving an accumulator, general registers and an instruction register in the arithmetic control unit.

Growing community of inventors

Tokyo, Japan

Tsuneo Kinoshita