Other

Kabushiki Kaisha Toshiba

Fuji Xerox Co., Ltd.

Kyocera Corporation

Renesas Technology Corp.

Oki Semiconductor Co., Ltd.

Fujitsu Microelectronics Limited

Tama-tlo Corporation

Tsuneo Ito

Yutaka Akiyama

Yuko Tanba

Kanji Otsuka

Yoichi Sato

Tamotsu Usami

Shigeru Yamamoto

Fumio Mizuno

Takeshi Koyama

Munekazu Takano

Saburo Yokokura

Masahiro Yoshida

A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memoriesincluding basic cellsarranged in a cluster, the basic cellincluding a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memorieslocated along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibusincluding a through-via, an arbitrary one of the basic cellsis directly accessed through the multibusfrom the controller chip so that truth value data is written therein, and whereby the arbitrary basic cellis switched to a logic circuit as conjugate.

Memory/logic conjugate system

The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnectionfor transmission of signals, a MOS capacitance elementhaving a gate electrode connected to the signal-transmission interconnection, a first voltage-applying interconnectionconnected to a source and a drain of the MOS capacitance elementand applying a voltage to the source and the drain of the MOS capacitance element, a second voltage-applying interconnectionconnected to a well of the MOS capacitance element, and applying a voltage to the well of said first MOS capacitance element. Jitters occurring in the signal-transmission interconnectioncan be adjusted by adjusting each of voltages of the first voltage-applying interconnectionand the second voltage-applying interconnection

Semiconductor device and method for adjusting characteristics thereof

Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

Electrostatic discharge protection circuit and terminating resistor circuit

Growing community of inventors

Ome, Japan

Tsuneo Ito