Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Other

Skhynix Inc.

Tsuneo Inaba

Kenji Tsuchida

Shinichiro Shiratake

Dong Keun Kim

Masahiro Takahashi

Daisaburo Takashima

Masahiko Nakayama

Katsuaki Isobe

Ji Wang Lee

Tatsuya Kishi

Yoshihiro Ueda

Hisanori Aikawa

Dong-Keun Kim

Hiroyuki Takenaka

Masaharu Wada

Toshimi Ikeda

Takashi Maeda

Daisuke Watanabe

Toshihiko Nagase

Yoshiaki Asao

Atsushi Kawasumi

Takeshi Kajiyama

Naoharu Shimomura

Kazuya Sawada

Keisuke Nakatsuka

Takeshi Sonehara

Hideo Mukai

Ryousuke Takizawa

Hironobu Akita

Kiyotaro Itagaki

Masaru Toko

Young Min Eeh

Jyunichi Ozeki

Koichi Nakayama

Nobuyuki Ogata

Erika Kodama

Nobutaka Nakamura

Yoshiaki Fukuzumi

Noboru Shibata

Hiroshi Maejima

Hiroaki Yoda

Yoshihisa Iwata

Takashi Ohsawa

Atsushi Takeuchi

Yukihito Oowaki

Naoya Tokiwa

Eiji Kitagawa

Kuninori Kawabata

Takayuki Miyazaki

Shinji Miyano

Satoru Takase

Ji-Wang Lee

Sumio Ikegawa

Yuui Shimizu

Mutsumi Okajima

Akira Katayama

Toshiki Hisada

Toshifumi Hashimoto

Fumihiro Kohno

Takeshi Sugimoto

Yuki Inuzuka

Yasuyuki Fukuda

Yutaka Shirai

Hyuck Sang Yim

Shingo Nakazawa

Akihiko Chiba

Byoung Chan Oh

Mamoru Ishizaka

Kouji Tsuchida

Junichi Okamura

Takeshi Aoki

A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.

Semiconductor memory device

According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.

Semiconductor storage device

A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.

Semiconductor memory device having a plurality of memory cells each having a phase change material

According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.

According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.

Memory device

A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.

Magnetoresistive memory device with different write pulse patterns

A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.

Magnetic storage device with voltage generator that varies voltages according to temperature

According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.

According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.

A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

Resistance change type memory

A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.

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Kamakura, Japan

Tsuneo Inaba