Kabushiki Kaisha Toshiba

Toshiba Micro-computer Engineering Corp.

Tsuneo Hamai

Kazuo Suganuma

A semiconductor device has a multi-layer structure comprising three or more interconnect layers formed over a substrate, one of these interconnect layers being a first power supply line and another metal interconnect layer being a second power supply line, the first and second power supply lines being arranged in a multi-level fashion such that one is superposed relative to the other in a plan view. That is, the power supply lines are arranged as a multi-layer metal interconnect layer array such that the first and second power supply lines are superposed in a multi-level fashion in a plan view.

Semiconductor device having a multi-layer interconnect structure

A logic circuit, comprising a plurality of driver MOSFETs and one load MOSFET, produces an output signal responsive to input signals. The driver MOSFETs are each controlled by an input signal and the load MOSFET is controlled by one of input signals to conduct at opposite times to the driver MOSFET controlled by the same input signal. Therefore, a logic circuit with low power consumption and a small area is provided.

Growing community of inventors

Yokohama, Japan

Tsuneo Hamai