Sony Corporation

Sony Semiconductor Solutions Corporation

Tsunenori Shiimoto

Tomohito Tsushima

Makoto Kitagawa

Masaaki Hara

Shuichiro Yasuda

Nobumichi Okazaki

Yujiro Ito

Wataru Otsuka

Jun Sawai

Hiroshi Yoshihara

Tetsuya Yamamoto

Yasushi Fujinami

Katsuhisa Aratani

Kenichi Nakanishi

Ken Ishii

Takashi Shimizu

Hideaki Okubo

Tadaaki Yoshinaka

Tatsuo Shinbashi

Haruhiko Terada

Hiroyuki Iwaki

Hironobu Mori

Hidenari Hachino

Nobuchika Momochi

Chieko Nakashima

Kentaro Ogata

Matatoshi Honjo

Semiconductors and methods of manufacturing semiconductors are provided. A semiconductor can include a plurality of insulating layers, and a plurality of conductive layers, with the insulating layers and the conductive layers alternately stacked. A plurality of through electrodes penetrate the conductive layers. At least some the through electrodes are electrically connected to one of the conductive layers. In addition, different conductive layers are connected to different through electrodes. A method of forming a semiconductor structure includes providing a plurality of antifuses, wherein each of the through electrodes is separated from each of the conductive layers by an antifuse. The method further includes supplying at least a first voltage to a first through electrode while applying less than a second voltage to the other electrodes, wherein the first voltage is greater than the second voltage.

Semiconductor device and method of manufacturing the same

Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Storage control apparatus, storage apparatus, and storage control method

A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states.

Semiconductor device and information reading method

A semiconductor device includes; a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states.

Disclosed herein is a variable-resistance memory device including a first common line; a second common line; a storage element connected between the first common line and the second common line to serve as a storage element whose resistance changes in accordance with a voltage applied to the storage element; and a driving control circuit.

Variable-resistance memory device and its operation method

A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.

Storage apparatus and operation method for operating the same

A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

Memory apparatus

A non-volatile semiconductor memory device includes: a memory component in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one of the electrodes of the memory component is connected with a reference electric potential; and a load capacitance changing unit that changes load capacitance of a sense node of the sense amplifier to which the discharge electric potential is input or both the load capacitance of the sense node and load capacitance of a reference node of the sense amplifier to which the reference electric potential is input in accordance with the logic of the information read out by the memory component.

Non-volatile semiconductor memory device that changes a load capacitance of a sense node in accordance with a logic value of read information

Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodesandin a variable resistance element. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance elementmay be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance elementmay be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.

Method of stabilizing data hold operations of a storage device

A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node.

Nonvolatile semiconductor memory device

A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.

Memory device and method of reading memory device

A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased).

Storage device and information rerecording method

A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-bit recording is provided. An initial value of a potential difference VGS between a gate and a source of a switching transistor at the time of the verify is set to a value varied based on a resistance value level of multi-bit information. In the case of recording 2 bits when '01' is the information, an initial value VGSis set to be smaller than VGS=1.7 V corresponding to the target resistance value level '01', and when &#x201c;00&#x201d; is the information, a value is set to be lower than VGS=2.2 V corresponding to the target resistance value level &#x201c;00&#x201d; and higher than the above-described VGS. This can reduce the number of cycles necessary for the verify process.

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Kanagawa, Japan

Tsunenori Shiimoto