Hitachi, Ltd.

Hitachi Keiyo Engineering Co., Ltd.

Other

Hitachi Ulsi Engineering Corp.

Hitachi Engineering Co., Ltd.

Hitachi Chubu Software, Ltd.

Hitachi Ulsi

Tsunehiro Tobita

Ryuichi Hattori

Kunihiro Katayama

Kenichi Kaki

Jun Kitahara

Tsutomu Hara

Yukihiro Seki

Hideki Osaka

Takashi Oeda

Koichi Okazawa

Toshihiko Ogura

Takashi Totsuka

Takashi Tsunehiro

Takeshi Suzuki

Takeshi Wada

Hajime Yamagami

Takashi Kikuchi

Takao Okubo

Masamichi Kishi

Shigeru Kadowaki

Manabu Saito

Yosio Takaya

Ichiro Ote

Yuji Miyagawa

Shigeru Sakurai

Hiroshi Furukawa

Yuichi Kobayashi

Kazunori Furusawa

Teiji Karasaki

Hiroaki Washimi

Masami Murai

Shinichi Suzuki

Takashi Maruyama

Hideyuki Osakada

Hitoshi Yoshidome

Hiroshi Mochizuki

Junichi Taguri

Tetsuo Hiramitsu

Toshinobu Matsuoka

Yoshitsugu Ichieda

Hiroyuki Hodo

Mihoko Kudou

Michiyuki Suzuki

A problem to be solved is to enable the user to read out data stored in a logical unit in a power saving state in a short time in a storage system having a power saving function such as stopping the spindle of the HDD. To solve the problem, candidate document file information is read out according to the keywords inputted by the user from a search system, a predetermined number of document file names are extracted from the highest candidates in the candidate document file information, and the power saving function of the logical units actually storing the extracted document files is controlled (switch the state from the power saving state to the normal operation state).

Information processing system and program for controlling the information processing system

In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Data processing apparatus and network system that outputs quality of service information to a user

A computer management system attains, through one line, the uniform and steady system management through an agent such as monitoring of fault and power control in a computer connected by LAN as well as a public line, and system management for an off-state of the computer or abnormal operation state of the computer such as remote power control and notice and diagnosis of critical fault by the direct connection with a service processor through the line. The system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.

Computer management system

A flash memory based file memory device built in an information processing apparatus enables fast file access. The file memory device is provided with a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device and a data access width smaller than the data bus, a file division unit for dividing file data that consists of one or more unit storage data blocks into combined blocks that consists of a combination of arbitrary unit storage data blocks, a data distribution unit for combining arbitrarily data on the data bus in terms of the unit data size equal to the data access width and making the combined data correspondent to an arbitrary combination of memory element groups equal in number to the unit size data, and a control unit for controlling the data distribution unit such that each combined block is stored in the file memory device by being correspondent to one of the arbitrary combinations of memory element groups.

File memory device and information processing apparatus using the same

A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance. The file memory device includes a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device, and a data access width smaller than the data bus; a file division unit for dividing file data having one or more unit storage data blocks into combined blocks that include a combination of arbitrary unit storage data blocks; a data distribution unit for arbitrarily combining data on the data bus having a unit data size equal to the data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control unit for controlling the data distribution unit so that each combined block is stored in the file memory device based on a correspondence between the combined block and arbitrary combinations of memory elements.

Accessible network of performance index tables

A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.

Flash memory control method and apparatus processing system therewith

Information processing system having a network and a directory which may be referenced to supply information to an apparatus

A bus system has a bus constructed of a plurality of signal lines for transmission of signals, first and second terminating resistors provided at both ends of the respective signal lines, first, second and third modules coupled to the bus between the first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type, first series resistors inserted in the respective signal lines between the first and second modules, and second series resistors inserted in the respective signal lines between the second and third modules.

Bus system

A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.

File memory device using flash memories, and an information processing system using the same

A computer management system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.

Growing community of inventors

Yokohama, Japan

Tsunehiro Tobita