Kabushiki Kaisha Toshiba

Tsuneaki Kudou

Hiroyuki Watanabe

Takeji Tokumaru

Yasuyuki Nozuyama

Naoko Nakamura

Kazuyuki Omote

An information processing system composed of a plurality of circuit blocks operative in an normal operation mode and in a self-diagnosis mode comprises: a clock signal generating circuit for generating a basic clock signal in the normal operation mode, and a first clock signal with a period. N times (N=2, 3, . . . ) as long as that of the basic clock signal and a second clock signal out of phase from the first clock signal by a delay less than one cycle of the first clock signal in the self-diagnosis mode; a memory for storing microinstructions for self-diagnosis operative in synchronism with the basic clock signal in the normal operation mode, and in synchronism with the first clock signal in the self-diagnosis mode; a decoder for inputting and decoding the mlcroinstructions for self-diagnosis stored in the memory; a test data generating circuit for generating test data in accordance with the decoded results obtained by the decoder in synchronism with the first clock signal at the self-diagnosis mode; first type circuit blocks operative in synchronism with the basic clock in the normal operation mode, for storing test data generated by said test data generating means In synchronism with the second clock and outputting test data therein In synchronism with the first clock In the self-diagnosis mode; second type circuit blocks for outputting output data corresponding to the test data provided in synchronism with the basic clock signal in the normal operation mode, and in synchronism with the first clock in the self-diagnosis mode; and a signature compressing circuit for inputting the test resultant data outputted from the circuit blocks to diagnose the operation of the circuit blocks, in synchronism with the second clock signal in the self-diagnosis mode.

Information processing system provided with self-diagnosing circuit and

A large scale standard cell is provided with at least three power source wires and at least two circuit-element-arranging areas interposed therebetween, whereby the lateral length of the cell can be flexibly reduced to owing delay due to wire resistance and capacity and to reduce the area of the cell or the entire area of a circuit pattern composed therewith. The vertical direction of the cell is optionally changeable in one cell row.

Standard cell layout arrangement for an LSI circuit

A read only memory includes a memory cell matrix, a word line decoder, a column decoder, and an output buffer. Said memory cell matrix is comprised of a plurality of submatrices, each of which is formed by dividing bit lines into a plurality of parts. Each sub-matrix contains the same word lines. Said word line decoder produces a signal to select a certain sub-matrix in addition to signals to select a certain word line. Said column decoder produces signals to select one column from each of said sub-matrix. Said output buffer has a column selection circuit having a plurality of stages. The first stage selects one column from each of said sub-matrices according to said signals from said column decoder. The second stage selects one column among said selected columns according to said signal to select a certain sub-matrix produced in said word line decoder. Thus, a particular memory cell is selected from the memory cell matrix. In this case, the number of memory cell transistors connected to each bit line is greatly reduced. The data readout speed of this ROM is, therefore, greatly improved in this invention.

Read only memory

A first bus wiring line to which a plurality of first circuits each having the same bit range are connected, a second bus wiring line to which a plurality of second circuits each having a bit range smaller than that of each of the first circuits are connected, and a bus interface circuit having a buffer circuit connected between a portion of the first bus wiring line and the second bus wiring line and a dummy buffer circuit connected to the remaining portion of the first bus wiring line are arranged in an integrated circuit. Fox this reason, when a plurality of circuits having different bit ranges are connected to the bus wiring lines, the loads of the bus wiring lines can be made uniform, and a data transfer operation through the bus lines can be performed at a high speed. The operating frequency of a clock can be increased, and the performance of the system can be improved.

Bus interface circuit for connecting bus lines having different bit

An integrated circuit with circuit layout enabling higher area utilization efficiency and shorter routing lengths, suitable for large-scale integrated, high-speed processing applications. The integrated circuit includes at least one function block for performing desired functions with respect to input data entered in a first direction to produce output data in the first direction; and at least two control blocks for providing control signals for controlling the operations of the function block, in a second direction perpendicular to the first direction, the control blocks being arranged such that the function block is located between two of the control blocks.

Integrated circuit with layout effective for high-speed processing

Disclosed herein is an adder which comprises a Manchester-type adder circuit and which can operate as fast as a dynamic adder, and can perform addition during the clock cycle as a static dynamic adder. Hence, the adder serves to increase the operating frequency of the system in which it is incorporated. The adder further comprises two initializing signal output circuits, each designed to generate an initializing signal in response to predetermined data supplied before the Manchester-type adder circuit starts performing each operation, thereby to initialize the Manchester-type adder circuit.

Adder circuit having carry signal initializing circuit

An improved flip-flop with a scan path comprises a front page circuit driven in response to a clock signal and multiplexers for receiving a data signal and a scan test signal. Each of the multiplexers comprises a single stage of FETs connected in series between a power source and a ground. This arrangement can remarkably improve an operation frequency.

Flip-flop with scan path

A standard cell for standard-cell type integrated circuits, designed with a computer, includes a basic functional circuit, for example, a flip-flop circuit and a signal delay circuit connected to the basic functional circuit. The signal delay circuit is located within the standard cell along with the basic functional circuit. The design allows the timing of the integrated circuit to be adjusted without changing the geometry of the integrated circuit.

Standard cell and standard-cell-type integrated circuit

A dynamic barrel shifter has a data input portion, a data shift portion, and a shifted data output portion including sense inverters which are set at threshold voltage higher than a half of the power source voltage. The sense inverters are provided for every transmission route for each binary code. The dynamic barrel shifter also has a pre-charge portion for pre-charging the data shift portion and the shifted data output portion prior to the input of data. The pre-charge portion includes a first power source voltage applying circuit for applying electric potential lower than the power source voltage to the data shift portion through first gate elements from the power source, and a second power source voltage applying circuit for applying electric potential equal to the power source voltage to the input side of the shifted data output portion through second gate elements.

Dynamic barrel shifter

A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.

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Yokohama, Japan

Tsuneaki Kudou