Kabushiki Kaisha Toshiba

Toshiba Corporation

Tsuneaki Fuse

Yukihito Oowaki

Koji Sakui

Fujio Masuoka

Shigeyoshi Watanabe

Haruki Toda

Takehiro Hasegawa

Masahiro Kamoshida

Toshiki Seshita

Akihiro Nitayama

Fumio Horiguchi

Atsushi Kameyama

Masako Yoshida

Seiichi Aritome

Takashi Yamada

Kazunori Ohuchi

Shigeru Kawanaka

Tomoaki Shino

Kazumi Inoh

Makoto Yoshimi

Hideaki Nii

Masako Ohta

Sadayuki Yoshitomi

Katsuhiko Hieda

Kenji Numata

Kazumasa Sunouchi

Seiro Imai

Mamoru Terauchi

Masaki Ichikawa

Yoko Shuto

Satomi Nakano

A reference current generating circuit includes first and second standard current generating circuits to generate first and second standard currents, respectively and first and second trimming circuits to generate first and second reference circuits by trimming the standard current values outputted from the standard current generating circuits. The second standard current generating circuit operates for a part of an operation period of the first standard current generating circuit. The value of the first reference current is compared with a value of the second reference current, and controlled so as to approach the value of the second reference current by a trimming controller.

Reference current generating circuit

A sense amplifier control circuit includes an initial-voltage setting circuit configured to set a control signal to an initial voltage, the control signal controlling a sensing operation of a sense amplifier, and a control-signal-level adjusting circuit configured to first change a voltage level of the control signal from the initial voltage to a voltage level at which the sense amplifier can execute a current sensing, and is configured to second change, after a predetermined time elapses, the voltage level at which the sense amplifier can execute the current sensing to a voltage level at which the sense amplifier can execute a voltage sensing.

Sense-amplifier control circuit and controlling method of sense amplifier

A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.

Semiconductor device

A semiconductor integrated circuit of an aspect of the present invention having a CMOS logic gate including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, has a first MOS transistor region in which the first MOS transistor is formed, and a 2ath MOS transistor region and a 2bth MOS transistor region, in each of which the second MOS transistor is formed, separately arranged to be in contact with a first side of said first MOS transistor region and a second side opposite to the first side.

Semiconductor integrated circuit including CMOS logic gate

An integrated circuit has first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a high threshold value, while the second logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a low threshold value. An output switch circuit intervenes between the p-type FET and n-type FET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.

Semiconductor integrated circuit

Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N&plus;1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N&plus;1)th stage, wasteful consumption of electric power is prevented.

Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal

A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.

Level converter circuit

A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.

A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.

Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal

A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse width of A. Consequently, as forward pulse becomes &ldquo;H&rdquo; while pulse s is &ldquo;L&rdquo; without generating pulse which width is narrower than A, the edge part of forward pulse is securely propagated by a forward-pulse delay line even if it is high frequency. Propagation of forward pulse stops at rising edge of pulse s, and rearward pulse is generated in a corresponding stage. This rearward pulse is propagated by a rearward-pulse delay line, and outputted from an output buffer. As each delay element of forward-pulse delay line and rearward-pulse delay line is configured with one-gate circuits, propagation time of forward pulse and rearward pulse can be adjusted to the time (&tgr;&minus;A) with high accuracy to improve synchronization accuracy.

Clock control circuit

In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Lateral bipolar transistor formed on an insulating layer

Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

Dynamic random access memory device

A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition I,<I,according to a voltage applied across a base and emitter where I,is the base current flowing through a base-emitter path in a forward direction, and I,is the base current flowing through a collector-base path in a reverse direction.

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Tokyo, Japan

Tsuneaki Fuse