Western Digital Technologies, Inc.

Western Digital Corporation

Tsun Y Ng

Virgil V Wilkins

Ralph H Castro

Quoc Dang

Kenneth J D'Souza

The present invention relates to a disk drive including a cache memory having a plurality of sequentially-ordered memory clusters for caching disk data stored in sectors (not shown) on disks of a disk assembly. The disk sectors are identified by logical block addresses (LBAs). A cache control system of the disk drive comprises a cluster control block memory, having a plurality of cluster control blocks (CCB), and a tag memory, having a plurality of tag records, that are embedded within the cache control system. Each CCB includes a cluster segment record with an entry for associating the CCB with a particular memory cluster and for forming variable length segments of the memory clusters without regard to the sequential order of the memory clusters. Each tag record assigns a segment to a continuous range of LBAs and defines the CCBs forming the segment. Each segment of the memory clusters is for caching data from a contiguous range of the logical block addresses. The cache control system efficiently exploits available memory clusters for responding to host commands.

Cluster-based cache memory allocation

The present invention relates to disk drive having a cache control system that generates scan results that permit response to a host command using existing cached data having a logical block address (LBA) range that overlaps a host command LBA range. The cache control system forms variable length segments of memory clusters in a cache memory for caching disk data in contiguous LBA ranges. The cached LBA ranges are scanned for segments having LBA ranges overlapping with an LBA range of a host command. The cache control system is effective in exploiting any existing overlapping cache data.

Range-based cache control system and method

The present invention is embodied in the disk drive having a cache control system that is configured to efficiently respond to host commands by forming variable length segments of memory clusters for caching disk data in contiguous ranges of logical block addresses without regard to the sequential order of the memory clusters. The cache control system has a tag memory usable only for defining the segments. The tag memory has a plurality of tag records pointing to cluster control blocks associated with the memory clusters for defining the segments. The tag memory may be accessed and updated by several state machines in the cache control system and by a microprocessor in the disk drive.

Tag memory disk cache architecture

The present invention relates to a disk drive comprising a cache memory and a cache control system having a tag memory having a plurality of tag records, and means for allocating a tag record for responding to a host command. The cache memory has a plurality of sequentially-ordered memory clusters for caching disk data stored in sectors (not shown) on disks of a disk assembly . Conventionally the disk sectors are identified by logical block addresses (LBAs). The cache control system along with the tag memory and means for allocating tag records are embedded within the cache control system and thereby configured only for use in defining variable length segments of the memory clusters . The segments are defined without regard to the sequential order of the memory clusters

Cache control system and method having hardware-based tag record allocation

The present invention relates to a disk drive including a cache memory having a plurality of sequentially-ordered memory clusters for caching disk data stored in sectors (not shown) on disks of a disk assembly. The disk sectors are identified by logical block addresses (LBAs). A cache control system of the disk drive comprises a cluster control block memory, having a plurality of cluster control blocks (CCB), and a tag memory , having a plurality of tag records, that are embedded within the cache control system. Each CCB includes a cluster segment record with an entry for associating the CCB with a particular memory cluster and for forming variable length segments of the memory clusters without regard to the sequential order of the memory clusters. Each tag record assigns a segment to a continuous range of LBAs and defines the CCBs forming the segment. Each segment of the memory clusters is for caching data from a contiguous range of the logical block addresses.

The present invention relates to disk drive having a cache control system that generates scan results that permit response to a host command using existing cached data having a logical block address (LBA) range that overlaps a host command LBA range. The cache control system forms variable length segments of memory clusters in a cache memory for caching disk data in contiguous LBA ranges. The cached LBA ranges are scanned for segments having LBA ranges overlapping with an LBA range of a host command.

A read-only memory is connectable to a microcontroller data bus and address bus and includes memory circuits for storing a sequential array of code words executable by the microcontroller; memory address decoding circuits for selecting one of the array of code words, and circuits for conveying the selected one to the data bus when a read signal is received from the microcontroller. Circuits are provided for storing an address transmitted by the microcontroller when an address latch signal is received from the microcontroller, the stored address being connected to the memory address decoding circuits. The stored address is incremented each time a read signal is asserted. A microcontroller for executing a program stored sequentially in read-only memory comprises an address bus for providing a next program code word address to the read-only memory; circuits for providing an address latch enable signal to the read-only memory for latching the program code word address, and circuits for providing a read signal to the read-only memory. The address latch enable signal is suppressed when the next program code word address is consecutive with an immediately preceding program code word address. The microcontroller does not generate the address of the next program code word as long as the address of the next program code is consecutive with an immediately preceding program code word address. A disk drive controller includes both such microcontroller and a program code memory.

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Orange, CA, United States of America

Tsun Y Ng