United Microelectronics Corp.

Tsun-Lai Hsu

Hua-Chou Tseng

Jun-Hong Ou

Jui-Fang Chen

Tien-Hao Tang

Shiao-Shien Chen

Cheng-Chou Hung

Victor-Chiang Liang

Ji-Wei Hsu

Yu-Chia Chen

Ya-Nan Mou

Cheng-Wen Fan

Yu-Yee Liow

Tsuoe-Hsiang Liao

Chien-Chou Hung

Chia-Hung Chin

Ellis Lin

A method for producing a layout of a device in an integrated circuit before actually fabricated is provided. The method includes inputting at least one fixed parameter for the device for fabrication. And then, a first part of a set of variable parameters of a layout of the device is input. The complete set of the variable parameters is generated. It is checked whether or not the layout with the parameters is satisfying a requirement, wherein an end step is reached if the layout is accepted by the requirement, and a new part of the set of variable parameters as the first part being looping in the foregoing steps if the layout is not accepted by the requirement.

Method for producing layout of semiconductor integrated circuit with radio frequency devices

An inductor formed on a semiconductor substrate is provided in the present invention. The inductor comprises a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.

Inductor formed on semiconductor substrate

An inductor structure comprising a substrate; a plurality of insulation layers on the substrate; a first spiral electric conductive coil positioned in the insulation layers to form an inductor having a first direction of magnetic field; a second spiral electric conductive coil positioned in the insulation layers to form an inductor having a second direction of magnetic field, in which, the two or more inductors are independently positioned in a same 3-D space and have a good integration.

Inductor structure

A high coupling factor transformer and a manufacturing method thereof are provided. The transformer includes a primary winding and a secondary winding. The secondary winding is adjacent to the primary winding. The secondary winding and the primary winding induct with each other. The primary winding includes a plurality of first protruding portions, and the secondary winding includes a plurality of second protruding portions. The first protruding portions stretch to the secondary winding without electro-contact, and the second protruding portions stretch to the primary winding without electro-contact.

High coupling factor transformer and manufacturing method thereof

A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

Method for fabricating a transformer integrated with a semiconductor structure

A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Capacitor structure

A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Structure and fabrication method of electrostatic discharge protection circuit

An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.

Method of fabricating inductor and structure formed therefrom

A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well guard ring can be selectively interposed between the P substrate guard ring and the device to facilitate blocking substrate coupling effect.

Substrate isolation design

A fabrication method of an electrostatic discharge protection circuit is described, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

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Hsinchu Hsien, Taiwan

Tsun-Lai Hsu