Kabushiki Kaisha Toshiba

Tsukasa Shirotori

Kazutaka Nogami

Atsushi Kawasumi

Takayasu Sakurai

Yukihiro Urakawa

Shigeyuki Hayakawa

Kazuhiro Sawada

Tsuguo Kobayashi

A migration section conducting process migration for converting first layout according to a first design standard into second layout according to a second design standard and a designated transistor size; an extraction section extracting transistor sizes and parasitic capacitances from the first and the second layout; a delay calculation section calculating first delay time from the transistor size and the parasitic capacitance extracted from the first layout and a driving current value of a transistor based on the first design standard, and calculating second delay time from the transistor size and the parasitic capacitance extracted from the second layout and a driving current value of the transistor based on the second design standard; and an optimum value calculation section calculating an optimum value of the transistor size after the process migration in order that the second delay time becomes equal to the first delay time, are provided.

LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit

A cache memory automatically sets a low-, semi-, or high-speed mode operation according to a result of comparison between a half-period of a reference clock signal and a pulse width of a reference pulse signal provided by a reference pulse signal generator. Namely, a start signal generator generates a start signal used to access data memories, according to the frequency of the reference clock signal and a difference between the reference clock and pulse signals. According to the start signal and information indicating a hit tag memory, the cache memory dynamically switches the modes from one to another, without external instructions to the cache memory. In one embodiment, the cache memory is an n-way set associative cache memory having a plurality of data memories, and an enable signal is supplied only to a data memory associated with the hit tag memory when receiving hit information before a low speed mode start signal, or to all of the data memories when receiving the hit information after the high-speed mode start signal.

Cache memory system having high and low speed and power consumption

A cache memory system has an address register for storing a tag address and an index address of data to be accessed, a plurality of data memories for storing data corresponding to said index address, a plurality of tag memories corresponding to said data memories for storing tag addresses relating to said data stored in said data memories, and tag comparators corresponding to said tag memories for comparing a tag address stored in said tag memories with the tag address stored in the address register and for determining whether a cache hit has occurred or a cache miss has occurred. A reference frequency information register stores information indicating a tag memory which has resulted in a cache hit. An access control circuit selects one of the tag memories and one of the comparators corresponding to the selected tag memory based on the information from the reference frequency information register. Only the selected tag memory and the selected tag comparator are operated in order to control a comparison operation of tag addresses and to reduce power consumption.

Cache memory system with reduced tag memory power consumption

A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.

Semiconductor memory device employing sense amplifier control circuit

A semiconductor integrated circuit includes a plurality of writable/readable memory blocks with different address spaces and an address decoder for selecting addresses of the memory blocks. The multiple memory blocks are permitted to share a part of addresses of the memory blocks in a test mode. The writing operation of one of the memory blocks that does not have the largest address space is disabled during a period in which address signals for commonly performing an address scan of individual memory blocks exceeds the address width of that memory block. It is therefore possible to permit a plurality of memory blocks with different address spaces mounted on the same chip to be tested with high precision and without additional burden on the generation of test vectors or on a BIST (built-in self test) test circuit.

Semiconductor integrated circuit capable of testing memory blocks

An output circuit comprises an output transistor, a reference oscillator, a variable frequency oscillator, and a control circuit. The reference oscillator produces a first signal of a reference frequency according to the ideal ON resistance of the output transistor. The variable frequency oscillator generates a second signal capable of varying the oscillation frequency. The phase comparator compares the phase of a first signal from the reference oscillator with that of a second signal from the variable frequency oscillator and then controls the oscillation frequency of the variable frequency oscillator so that these two phases may coincide with each other. The control circuit controls the output transistor so that the current driving capability may be kept constant according to the output of the phase comparator.

High speed output circuit having current driving capability which is

A semiconductor device comprises a logic circuit and a memory including a timing signal generator circuit, both formed in a substrate, and a wiring connecting the logic circuit to the memory, in which a diffusion layers connected to receive a predetermined potential is located under an area of the wiring situated between the logic circuit and the memory whereby it is possible to alleviate an effect from minority carriers and a substrate potential variation.

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Yokohama, Japan

Tsukasa Shirotori