Mita Industrial Co., Ltd.

Tsukasa Matsushita

Hidechika Kumamoto

Haruo Yamamoto

Masaya Fujimoto

Ariyoshi Hikosaka

Hiroyuki Fujita

Akira Shimatani

Tetsuji Kajitani

Hideo Azumai

Shinobu Satonaka

Satoshi Iwatsubo

Takuji Okumura

Hidemitsu Hirano

In accordance with the present invention, a quadratic differential values is first calculated, based on differences in the density data between an object pixel and respective peripheral pixels around the object pixel. The square value SS of the quadratic differential value S and the sum .SIGMA.SS obtained by adding up the square values SS of quadratic differential values for continuous five pixels are employed as determination values (step n1). The square sum .SIGMA.SS is compared with respective threshold values a, b and d, and the square value SS is compared with respective threshold values c, e and f (steps n2 to n6 and n8). Based on these comparison results, it is judged which image area among a character image area, gray-scale image area and dotted image area the object pixel belongs to. As for the image area judgement concerning the dotted image area, the final judgement that the object pixel belongs to the dotted image area is made only when nine continuous pixels including the object pixel are all judged to belong to the dotted image area. Since the square values SS and square sum .SIGMA.SS take only a positive value, the threshold values are set only in a positive range, and hence the image processing can be simplified. Further, by employing the square sum .SIGMA.SS, the states of the peripheral pixels can be taken into consideration for the image area judgement.

Image processing method and apparatus

A skew processing circuit 33 includes two line buffers, a skew processing type line buffer 331 and an original type line buffer 332, and a write/read control circuit 333 for controlling the two line buffers. The write/read control circuit 333 is a control circuit for writing a given image data in the line buffers 331, 332 in single lines and selectively reading the data written in the two line buffers 331, 332. When an image data is written in the original type line buffer 332, addressed are sequentially written from the head address 0. On the other hand, when the image data is written in the skew processing type line buffer 331, a write start address RH0 is determined in correspondence with a skew angle, and the write start address RH0 is shifted in each line to discard the head portion of the image data by specified dots (specified addresses). Thus, by controlling the writing of data in the two line buffers 331, 332 and reading data from them, an image in an arbitrary area can be processed into the skew with an arbitrary angle.

Skew processing circuit and method of calculating a preset value for the

A laser beam controller comprises a basic pulse signal generating circuit, a delay circuit, a delay control circuit, a pulse generating circuit and a laser beam generator. The basic pulse signal generating circuit generates periodically occurring basic pulse signal. The delay circuit delays the basic pulse signal. The delay control circuit controls the delay time of the basic pulse in the delay circuit according to image data. The pulse generating circuit generates an output pulse having a width corresponding to the delay time of the basic pulse signal. The laser beam generator generates a laser beam for a duration corresponding to the width of the output pulse by said pulse generating circuit. According to the controller, any desired gradation of a pixel of the image is desirably produced.

Laser beam controller

An integrated circuit (IC) card for use in an image processing machine, such as a digital copying machine. The IC card includes a first storage area for storing data for controlling said image processor and a second storage area for storing image data to be processed by said image processor.

IC card for image processor

An enlargement/reduction signal generating apparatus comprises means for generating basic clock pulses, means for generating frequency-divided clock pulses of different kinds, having the different frequencies by dividing the frequency of said basic clock pulses, means for generating selection signals to combine said clock pulses generated by said basic clock pulse generating means and said frequency-divided clock pulse generating means, whereby the ratio of said reading clock pulses to said writing clock pulses corresponds to a predetermined enlargement/reduction ratio, and means for making enlargement/reduction clock pulses by combining said basic clock pulses and said frequency-divided clock pulses in correspondence with said selection signals from said selection signal generating means and for outputting said enlargement/reduction clock pulses as said reading clock pulses or said writing clock pulses. The enlargement/reduction signal generating apparatus is an apparatus for generating reading clock pulses and writing clock pulses to enlarge or reduce the image of digital data stored in a storing means. The apparatus may be disposed in an image processing unit for processing image information. The image processing unit may be used as a unit which receives image information from an optical unit, enlarges or reduces the image information, and outputs the enlarged/reduced image information to an image forming part, in a copying machine having a scanner and a printer. The copying machine may be a digital copying machine having a laser unit.

Apparatus for generating an enlargement/reduction signal

An image processing apparatus wherein a document on a document support table and an optical system are moved relative to each other for scanning to read the image of the document as a density signal, and the read signal is processed as required, the apparatus comprising a document mat so colored that when the document support table is covered with the mat, the read signal represents an intermediate color, discriminating device for judging whether the density signal represents the intermediate color to produce a binary signal, a memory having a memory capacity of l/n based on the density signal, a write control for causing the binary signal to be written in the memory device in synchronism with the scanning movement, and apparatus for determining the size of the document from the contents of the memory device.

Image processing apparatus

In an image forming apparatus including a digital image processing device, an overlay memory stores predetermined image data. The image data stored in the overlay memory is read at a predetermined timing in a predetermined cycle and composite data is made from the image data and image data outputted from a line memory. Since the image data stored in the overlay memory is read at the predetermined timing in the predetermined cycle, various kinds of overlaid image which may include a space-magnified image can be made by arbitrarily selecting the timing and cycle for reading.

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Osaka, Japan

Tsukasa Matsushita