Samsung Electronics Co., Ltd.

Tsukasa Matsuda

Shigenobu Maeda

Nae-in Lee

Byung-Hee Kim

Jin-Nam Kim

Jong-Jin Lee

Gilheyun Choi

Rak-Hwan Kim

Jongmyeong Lee

Hidenobu Fukutome

Jongmin Baek

Dohyoung Kim

Eun-Ji Jung

YoungWoo Cho

Euibok Lee

Jae-Won Hwang

Jeong-Ok Cha

Jung-Ha Hwang

Wan-Soo Park

Jongseo Hong

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Semiconductor device having a trench with a convexed shaped metal wire formed therein

A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

Semiconductor device and fabricating method thereof

In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

Methods of forming wiring structures including a plurality of metal layers

A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

Methods of manufacturing semiconductor devices including capped metal patterns with air gaps in-between for parasitic capacitance reduction

A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer.

Methods of forming metal patterns in openings in semiconductor devices

Growing community of inventors

Seongnam-si, South Korea

Tsukasa Matsuda