Kabushiki Kaisha Toshiba

Tsukasa Matoba

Mitsuo Saito

Takeshi Aikawa

Mitsuyoshi Okamura

Ken-ichi Maeda

Akihiro Kasahara

Hiroyuki Sakamoto

Yuichi Abe

Kenichi Maeda

Toshio Okamoto

Shinichi Matsukawa

Hiroyuki Satou

Yuuichi Kurosawa

Koichi Nishide

Motoshi Kurihara

Yuko Hagiwara

Naohiko Okamoto

In this content data delivery method, content data is transmitted from a content server to a first semiconductor device through a network. Then, the content data, content ID identifying the content data, and route data showing a route through which the content data is transmitted are transmitted from the first semiconductor device to a second semiconductor device using close-proximity wireless communication. Thereafter, the content ID and the route data are transmitted from the second semiconductor device to the content server. In addition, based on the route data, a reward corresponding to the content ID is calculated for the first semiconductor device, and the reward is provided to the first semiconductor device.

Content data distribution system, content data delivery method, and semiconductor device

A statement is embedded in a description of a circuit for design in hardware description language stored in a function description storage section, the above statement outputting messages that test items have been tested according to a procedure stored in a package storage section. A function simulation executing section executes simulations to store the above messages in a message storage section. A report output section determines every test whether all the test items have been tested or not, based on messages stored in a message storage section, and data denoting a correspondence relationship between test vector names stored in a test data storage section and test items which are tested according to the above messages and outputs report of the determination results.

Function test support system and function test support method and hardware description model

A bus bridge mutually connects a CPU bus to which a CPU and a corresponding cache memory having a write-back scheme are coupled, an I/O bus to which a bus master is coupled, and a main memory which is commonly accessed through the CPU bus or I/O bus. In response to an access request from the bus master to the main memory, a cache snooping section snoops a cache memory to see whether an address in the access request satisfies a cache hit or miss, and data corresponding to the address is dirty or clear. In response to a snooping result by the cache snooping section indicating that the cache hit has occurred and the data is dirty, a write-back control section writes back the data from the cache memory in the main memory. In the case where the access request indicates a read request, a data bypass section directly transfers the data from the cache memory onto the I/O bus while the write-back control section performs writing back. With this processing, data read processing from the main memory need not wait for completion of write-back processing with respect to the main memory. Therefore, even if a cache write-back operation is performed in response to a main memory access request from the bus master, the main memory access operation can be performed at a high speed.

System for simultaneously writing back cached data via first bus and

A computer is constituted by a plurality of CPUs having the same power consumption and the same performance. A system controller has an interrupt control section. The interrupt control section generates an interrupt with respect to a CPU to be set in the halt state in accordance with the type of power supply, the battery residual capacity, the temperature of each CPU, and the throughput of each CPU, or the system operation environment setting set by the user or system software. Alternatively, a computer is constituted by CPUs having different power consumptions and different performances. A CPU switching section switches CPUs to be simultaneously operated in accordance with the type of power supply for a system, the heat value of each CPU in operation, and the load state of each CPU in operation, or the system operation environment settings set by the user or system software.

Multi-processor power saving system which dynamically detects the

A computer system according to the present invention comprises a processor, a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority corresponding to the frequency of access by the processor to read each of the data items, a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority corresponding to each of the data items, and a controller including means for obtaining, when a cache miss has occurred, a priority corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor, and means for comparing the obtained priority with a priority of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.

Computer with a cache controller and cache memory with a priority table

In the interval stop clock mode, the stop clock generating circuit in the system controller generates a stop clock signal that alternates between the active state and the inactive state and supplies the signal to the CPU. This causes the CPU to alternate between a state where the CPU is stopped from executing an instruction and an instruction executable state. In such a computer system, an interrupt type sensing circuit senses various interrupt request signals generated in the system and determines the type of each interrupt request. A stop clock temporary stopping circuit controls the stop clock generating circuit so as to bring the stop clock signal in the inactive state for the period of time specified by the timer value stored in the register corresponding to the determined type of the interrupt request. With this configuration, the performance of the CPU is prevented from falling off in a case where a load is exerted on the CPU as a result of a hardware interrupt to the CPU having occurred in the interval stop clock mode.

Computer system and stop clock signal control method for use in the

An instruction cache and a data cache are formed with a 2-port structure, the first port of the instruction cache is exclusively used for readout of the contiguous instruction, and the second port thereof is exclusively used for readout of the branched instruction when the conditional branch instruction is executed. With this construction, two instructions which may be executed can be simultaneously fetched irrespective of whether the branch of the conditional branch instruction is taken or untaken, thereby making it possible to enhance the CPU performance. Further, in the 2-port data cache, time for the cache refill process can be reduced by means of the contiguous data transfer and non-cacheable access.

Cache memory system having a plurality of ports

A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place. The device may alternatively include an address latch means for delaying transmission of a processor address from the processor to the data memory means by a predetermined number of process cycles when access by the processor is for a data-write process; and a data latch means for delaying transmission of a processor data from the processor to the data memory means by the predetermined number of process cycles when access by the processor is for a data-write process.

Cache memory device with fast data-write capacity

Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a 'back-up cell' for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein. The original register information is held in the first cell, thereby eliminating necessity of saving the original register information to a main memory at this stage. When the original register information is required again, the original register information can be rapidly restored, by only selecting the first cell again, in the corresponding register without executing save/restore processing between the register unit and the main memory.

Device for saving and restoring register information

A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.

Cache memory device constituting a memory device used in a computer

A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

Register device

A presentation display apparatus including a data storage section for storing a plurality of explanative image data each having (R), (G) and (B) color image components, a data processing section for adding, to the explanative image data from the data storage section, function select image data different in color component from the explanative image data, an image memory for storing the image data of one screen image output from the data processing section, a listener's first display device for displaying the image data which is delivered from image memory and a speaker's second display device. The image data output from the image memory is supplied through a first color converter to the listener's display device and through a second color converter to the speaker's display device. In the first color converter, the explanative image data is alone directly delivered as conversion image data in spite of function select menu image data, so that only the explanative (R)/(G)/(B) image is displayed on the listener's display device. In the second converter, the (R)/(G)/(B) input data are directly output as conversion image data when the function select image data is '0' and otherwise converted to all '1' when the function select menu image is '1' so that the function select menu and (R)/(G)/(B) explanative image are overlappingly displayed on the second display device.

Presentation display apparatus for displaying two different images on

A position and image inputting unit in accordance with the present invention is a unit in which both the position inputting function and the image inputting function are incorporated in a packing case. The unit may be used for inputting the position data, as in a mouse in the prior art, when the user presses the packing case lightly. For inputting an image, the packing case is to be pressed harder, and the packing case is moved in the direction perpendicular to the scanning direction of the image scanner. To facilitate the motion, there is provided a guiding roller so that when the packing case is pressed hard, the case moves in a fixed direction only. Furthermore, in this state, through the operation of the image scanner, the image data is scanned and input in succession in the direction perpendicular to the direction of motion of the packing case.

Growing community of inventors

Kawasaki, Japan

Tsukasa Matoba