Sharp Kabushiki Kaisha Corporation

Tsukasa Doi

Katsuji Iguchi

Masanori Murakami

Yufeng Weng

Takeo Oku

Mitsunobu Kimura

Seizo Kakimoto

Shigeo Ohnishi

Naoyuki Shinmura

Yushi Inoue

Takanori Sonoda

Shin Shimizu

Kazumasa Mitsumune

Kenichiroh Abe

Yukiko Mori

Light emitting diode

It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of &#x2267;3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N&#x2014;H bond density of the silicon nitride film is 1.0&#xd7;10pieces/cmor less. According to the method for forming the interlayer insulation film of the present invention, the occurrence of the voids can be suppressed in the interlayer insulation film even if the aspect ratio of the step part formed on the semiconductor substrate is 3 or more. Also, the damage applied to the semiconductor device by reflow can be reduced.

Method for forming interlayer insulation film

A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the second dielectric film and the semiconductor substrate.

Method of forming a device isolation region

A semiconductor device including, a wiring layer whose main component is copper being formed on a base via a barrier layer of amorphous tantalum carbide.

Semiconductor device having a copper wiring layer formed on a base via a

A semiconductor device comprises a plurality of transistors A semiconductor device comprising a plurality of transistors formed on a semiconductor substrate and a metal interconnection layer connected to at least one of the transistors, wherein the metal interconnection layer is composed of a single layer or multi layers, the single layer or at least one layer of the multi layers being formed of copper or a copper alloy, and is connected to at least one transistor wholly or partially through a barrier layer; and at least one of the transistor is controlled on its threshold voltage by a selective ion implantation after formation of the metal interconnection layer.

Method for fabricating a semiconductor device having copper layer

There is provided a semiconductor device manufacturing process which enables film deposition at low temperatures and can produce an interlayer insulating film of good quality which exhibits good surface smoothing effect. In the TEOS-O.sub.3 system normal pressure CVD process, film growth is carried out by adding to TEOS source a source containing nitrogen in its composition. For the source is used heptamethyl disilazane (chemical formula (CH.sub.3).sub.3 SiN(CH.sub.3)Si(CH.sub.3).sub.3), N, O-bis-trimethylsilyl acetamide (chemical formula (CH.sub.3)C(OSi(CH.sub.3).sub.3)(NSi(CH.sub.3).sub.3)) or tridimethylamino silane (chemical formula (CH.sub.3).sub.2 N).sub.3 SiN). Also, there is provided a semiconductor device manufacturing method which enables film deposition at a uniform growth rate irrespective of the substrate material and can produce a silicon oxide film of good quality which exhibits good surface smoothing effect. An organic source having an Si--N bond in its composition and O.sub.3 are conducted to the substrate and reacted with each other under normal pressure whereby a silicon oxide film is grown on the substrate. The organic source is, for example, hexamethyl disilazane ((CH.sub.3).sub.3 Si--N(H)--Si(CH.sub.3 ).sub.3).

Normal pressure CVD process for manufacture of a semiconductor device

A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and the gate electrode, the portion of the drain-side active region which overlaps with the second impurity-implanted region functioning as a drain region for the MOS transistor.

Growing community of inventors

Kitakatsuragi, Japan

Tsukasa Doi