X-fab Semiconductor Foundries Ag

Tsui Ping Chu

Poh Ching Sim

Hyung Sun Yook

Brendan Toner

Evie Siaw Hei Kho

Foo Sen Liew

Yong Kheng Ang

Peng Yang

Swee Hua Tia

A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

MOS device assembly

A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors.

Capacitor structures for semiconductor device

A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.

Reduction of fluorine contamination of bond pads of semiconductor devices

In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

Growing community of inventors

Kuching, Malaysia

Tsui Ping Chu