Matsushita Electric Industrial Co., Ltd.

Tsuguyasu Hatsuda

Seiji Yamaguchi

Isao Tanaka

Tamotsu Nishiyama

Keiichi Kusumoto

Takashi Taniguchi

Toshiyuki Moriwaki

Tetsurou Toubou

Toru Kakiage

Naofumi Takagi

Kazuyuki Nakanishi

Akio Hirata

Hiroo Yamamoto

Ichirou Matsuo

Osamu Taketoshi

Miwa Ito

A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.

Signal transmission circuit

In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit. Accordingly, even when at least one of the amplitude voltage of the input signal and the amplitude voltage of the output signal is changed, balance between the fall delay time characteristic and the rise delay time characteristic of the output signal can be satisfactorily kept.

Level shifter having automatic delay adjusting function

In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.

Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library

Method and apparatus for calculating delay for logic circuit and method

A semiconductor memory device 200 includes: a memory cell array 101 including a plurality of pairs of bit lines (BL, XBL), a plurality of word lines WL and a plurality of memory cells 100; a decoder 104 for decoding address information to activate one of the plurality of word lines WL in accordance with the address information; precharge circuits 105 for setting each of the plurality of pair of bit lines (BL, XBL) to a predetermined precharge potential; sense amplifiers 110; and potential difference transmission circuits 109 provided between the memory cell array 101 and the sense amplifiers 110. The potential difference transmission circuits 109 hold a potential difference V.sub.d0 between respective pair of bit lines among the plurality of pairs of bit lines (BL, XBL) and transmit the held potential difference V.sub.d0 between the pair of bit lines to a respective sense amplifier 110. The sense amplifier 110 amplifies the potential difference V.sub.d0 between the pair of bit lines transmitted by the potential difference transmission circuit 109 so as to output the data stored in a corresponding memory cell.

Potential difference transmission device and semiconductor memory device

The level shift circuit of this invention includes two reference voltage level generation devices, and a difference between two reference voltage levels generated by these reference voltage level generation devices is used as a level shift voltage to be analog-added to an input analog signal. At least one of the two reference voltage level generation devices has a function to change the reference voltage level thereof in accordance with a supplied offset voltage adjusting signal, thereby changing the level shift voltage to be analog-added to the analog signal in accordance with the offset voltage adjusting signal. Thus, the level shift circuit achieves a function to adjust an offset voltage. When this level shift circuit is applied to a signal waveform generator, there is no need to provide the offset voltage adjusting function to a D/A converter. As a result, the power consumption as well as the circuit area of the signal waveform generator can be decreased.

Level shift circuit for analog signal and signal waveform generator

When a data is read out from a memory cell, a current mirror circuit is operated in response to detection of potential variation of a first data line, so that charge of a second data line is discharged by the current mirror circuit. At this point, a control transistor interposed between the first data line and the second data line is operated in a saturation region. As a result, the impedance between the first data line and the second data line becomes substantially infinity, and the two data lines are substantially open-circuited. Thus, the current mirror circuit discharges merely the second data line with a small load capacitance in a short period of time, resulting in a high speed read operation. Therefore, even when the first data line, to which a large number of memory cells are connected, has a large load capacitance, the read rate is increased.

Data read circuit used in semiconductor storage device

The present invention discloses the structure of a MIS capacitor adapted to be interposed between two terminals, i.e., first and second terminals, to be connected to an electric circuit. Formed on a common semiconductor substrate are first and second capacity insulator layers, first and second electrically conductive layers thereon, and first and second impurity diffusion areas under the first and second capacity insulator layers. Also formed are a first wiring line which connects the first electrically conductive layer and the second impurity diffusion area to the first terminal, and a second wiring line which connects the second electrically conductive layer and the first impurity diffusion area to the second terminal. Accordingly, the first electrically conductive layer and the second impurity diffusion area form one electrode, while the second electrically conductive layer and the first impurity diffusion area form the other electrode. With the arrangement above-mentioned, voltage dependencies inherent in capacitors each having a MIS structure are substantially cancelled with each other, resulting in reduction of the voltage dependency of the MIS capacitor. Through a process using one polysilicon layer, there can be formed an economical MIS capacitor having a small area which can be mounted on an analog circuit.

MIS capacitor and a semiconductor device utilizing said MIS capacitor

In the present invention, there are disposed (i) a P-channel MOSFET for detecting variations of the voltage level of a data line to supply an electric current, and (ii) a current mirror circuit to which an electric current from the P-channel MOSFET is entered as a reference current and of which output current terminal is connected to the data line. When the data line is lowered in voltage level so that an electric current flows from the P-channel MOSFET to the current mirror circuit, an output current of the current mirror circuit flows to the drain of an N-channel MOSFET, so that the data line is electrically discharged. Thus, there is achieved a sensing circuit unit which is suitably used for a dynamic circuit and which can detect, at a high speed, variations of the voltage level of the data line as precharged.

Sensing circuit unit for a dynamic circuit

A sample and hold circuit has an analog switch, a hold capacitor, a voltage-follower type operational amplifier, and a ringing cancel circuit. The ringing cancel circuit is interposed between a non-inverted input terminal of the operational amplifier and a signal ground so that the ringing cancel circuit is connected in parallel with the hold capacitor. The ringing cancel circuit is made up of a resistance and a capacitor connected in series with each other. With this arrangement, a high-speed, highly accurate, low power consumptive sample and hold circuit can be realized.

Sample and hold circuit

Plural memory cells are connected to a common word line. Provided in each memory cell are a bit line pair, a data line pair, a precharge circuit, a switch circuit, a timing control circuit, and a sense amplifier. Each timing control circuit provides a word line control signal and a switch control signal, before the output of the sense amplifier becomes definite and at a point in time when the potential of the bit line pair changes to such an extent that the sense amplifier becomes operatable. The switch control signal is applied to a corresponding switch circuit to separate the sense amplifier from the bit line pair. The word line control signal From each timing control circuit is applied to a single OR gate. The output of the OR gate, along with the output of a row decoder, is applied to an AND gate. The AND gate controls the word line for activation. When every word line control signal becomes LOW, the word line is made inactive to separate all the memory cells from the corresponding bit line pairs.

Semiconductor memory

A comparator for comparing the voltages of an address pair signals in complement with the voltages of bit pair signals in complement includes a pair of transistors for receiving the bit pair signals and a pair of MOSFETs for receiving the address pair signals. One transistor and one MOSFET are connected in series to define a first current path and other transistor and other MOSFET are connected in series to define a second current path. When the address signal and the bit signal are the same, both the first and second current paths close, but when they are different, either the first or the second current path opens to permit a current to pass therethrough. By detecting the current in the path, the coincidence and non-coincidence between the address pair signals and bit pair signals are detected.

Comparator using XNOR and XOR gates

The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.

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Osaka, Japan

Tsuguyasu Hatsuda