Hitachi, Ltd.

Tsuguo Shimizu

Kenichi Wada

Akira Yamaoka

Yooichi Shintani

Tsuguo Matsuura

Shunichi Torii

Chihei Miura

Naohiro Kageyama

Takashi Okada

Toru Shonai

Yoshio Takamine

Hiroyuki Nakajima

Kazuhiko Iijima

Rikako Kuroda

Rikako Suzuki

Yoichi Shintani

An automatic logic designing method and system in which a control table describing a condition and a behavior corresponding to the condition which express the specification of a computer is inputted and processed in a processor so that a logic circuit having no redundancy which can be easily seen by the designer is designed at a high speed. The control table is converted into the logic circuit whose function is expressed by a detailed Boolean expression. In an instance, selector logics are allocated in consideration of the polarity of the logic. A redundancy detection process or a redundancy logic elimination process is executed for the redundancy logics designated by a redundancy indicate file. A signal name which can be easily understood by the logic designer is formed. An implementing system includes an input control table file, a functional structure converting section of a conditional equation and a behavioral structure, a regular logic expanding processing section, and a redundancy logic elimination processing section, so that the logic circuit formed is outputted to a Boolean expression file.

Automatic logic designing method and system

A logic circuit the functions of which have been expressed by a Boolean expression is subdivided, and then each of the subdivided logic circuit portions corresponds to each of the Boolean expressions. A plurality of logic circuits whose functions are equal to each other, whose delay times and gate numbers are different from each other, are synthesized every subdivided circuit portions, and a restriction condition formula is formed by employing the synthesized logic circuit under a restriction condition of the delay time designated by a user. While a linear programming is applied under the restriction condition and the number of gates is used as an objective function, such a logic circuit that the objective function takes a stationary value (a minimum value in the present invention) is selected with respect to each of subdivided portions, whereby an overall logic circuit is constructed.

Logic synthesis method

In automatically synthesizing pipeline control, a first circuit indicates the data holding status of a register in response to a circuit description. A second circuit designates the register to receive output of a preceding register in response to the first circuit. A third circuit designates the preceding register to receive input in response to the first circuit without a circuit that indicates the data holding status of the preceding register. Logic responds to: a first file storing circuit description and data propagation behavior; a second file storing register data holding condition and status; and a third file storing logic templates that indicate whether data can be stored by the register, data holding status of the registers, data holding cycles of the registers, and cancel condition of data holding by the registers. The logic templates are assigned for the registers stored in the first file based on the contents of the second file. The element number of the assigned template and mutual connections are defined based on the second file. Based on the second file, determination is made of those registers that may really develop resource conflict among the points where the data meet together and the points where the wait factors of the data transfers develop as well as only those registers which will be affected by the resource conflict. Logic is generated by assigning templates to the thus determined registers, making it possible to suppress the generation of redundant logic.

Automatic logic generation method for pipeline processor

Herein disclosed is an automatic design system for automatically generating a data structure, which is only implicitly expressed by a logic specification description, by deriving, in case a logic system has data structures of similar constructions, one data structure from the structure description and transfer behavior description of the other data structure.

Automatic logic design system

A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

Data processing system

In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.

Buffer storage including a swapping circuit

A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.

Pipelined data processing system

In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.

Digital data processor with two operation units

A multiprocessor system includes a plurality of central processing units (CPUs), which have a main storage in common, and a key storage for storing therein control information for storage protection of, reference to, and change in the main storage. Each CPU is provided with the key storage, the CPUs are connected by interface lines so as to form a ring-like combination, a CPU in which a key access request is generated, carries out the key processing for its own key storage and supplies the interface line with an address, data and others which are contained in the key access request, and another CPU receives the address, data and others to perform the key processing for its own key storage. A signal for determining the priority among key access requests simultaneously generated in a plurality of central processing units circulates through the CPUs via the interface lines, one of the CPUs having generated the key access requests catches the priority determining signal to make its own key access request valid, and prevents the circulation of the priority determining signal for a time till the key processing based upon the valid request has been completed.

Data processing system having ring-like connected multiprocessors

This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed circular path. Each CPU has a cache buffer memory and two sets of transfer registers for receiving and transmitting cancel request signals which identify cache data which is no longer valid. Each CPU's receiving register subsystem includes circuitry for invalidating cache buffer data which has been updated or rewritten in main memory by another CPU in the loop. Each CPU's transmitting register subsystem includes circuitry for inhibiting the transmittal of a cancel request signal if the next CPU in the circle is the same one which originated the particular cache invalidation signal. Circuitry is also provided for propagating a cancel request signal around the loop in opposite directions simultaneously.

Multiprocessor system with apparatus for propagating cache buffer

A multiprogrammed data processing system with reduced processing time for interlock instructions compares the first partial address contained in a request with a corresponding first partial address of an interlocked address in a first comparator when a main storage control unit receives the request from one of central processing units. The main storage control unit sends the request to a main memory in response to non-coincidence signal from the first comparator. In response to a coincidence signal from the first comparator, the main storage control unit compares a second partial address contained in the request with a corresponding second partial address of the interlocked address. The main storage control unit sends the request in response to a non-coincidence signal from the second comparator.

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Sayama, Japan

Tsuguo Shimizu