Fujitsu Corporation

Fujitsu Semiconductor Limited

Tsuguchika Tabaru

Ryuichi Ohzeki

Toshihiro Suzuki

Manabu Matsuyama

Koji Ishihara

Tetsuo Kawano

Shinichi Sutou

Kiyomitsu Katou

Kyoji Sato

Masato Kondo

Hayato Higuchi

Katsumoto Nomimura

An apparatus includes a processor coupled to a memory and configured to extract a class in which a constructor or an assignment operator included in source code or a combination of the constructor and the operator is used, identify a call to the constructor or operator or the combination, calculate the number of times of access to member variables, indicated in the call identified and a periphery of the call; compare the number, calculated, of times of the access with the number of times of memory access, and generate intermediate code having, added thereto, information to be used to execute a process for copying the constructor or the operator or the combination in units of member variables, and generate intermediate code having information added thereto based on the call when the number, calculated, of times of the access is smaller than the number of times of the memory access.

Information processing device and compilation method

An arithmetic processing apparatus includes a plurality of arithmetic cores configured to execute threads in parallel, and a control unit configured to cause the arithmetic core to execute a reduction operation for data of the threads having the same storage area to which data is written per a predetermined number of threads in order to add data obtained by the reduction operation to data within a corresponding storage area by an atomic process.

Arithmetic processing apparatus, control method of arithmetic processing apparatus, and a computer-readable storage medium storing a control program for controlling an arithmetic processing apparatus

A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.

Data conversion apparatus, method, and computer-readable recording medium storing program for generating circuit configuration information from circuit description

A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as 'PE' hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.

Dynamic reconfiguration supporting method, dynamic reconfiguration supporting apparatus, and dynamic reconfiguration system

A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration.

Growing community of inventors

Kawasaki, Japan

Tsuguchika Tabaru