Hitachi, Ltd.

Nec Corporation

Elpida Memory, Inc.

Texas Instruments Corporation

Nikon Corporation

Other

Hitachi Device Engineering Co., Ltd.

Nan Ya Technology Corporation

Hitachi Vlsi Engineering Corp.

Rising Silicon, Inc.

Tsugio Takahashi

Tomonori Sekiguchi

Kazuhiko Kajigaya

Riichiro Takemura

Katsutaka Kimura

Goro Kitsukawa

Takesada Akiba

Yasushi Kawase

Masayuki Nakamura

Yoshitaka Nakamura

Shunichi Sukegawa

Masayuki M Nakamura

Yoshio Imura

Hitoshi Aoki

Hidenori Miyamoto

Hiroki Fujisawa

Hideya Inoue

Daiki Tsukahara

Tatsuya Murakami

Noriyasu Kotani

Hidefumi Masuzaki

Yukihide Suzuki

Kazunori Kinoshita

Jun Nagai

Masashi Horiguchi

Koichi Abe

Kouji Arai

Tsutomu Takahashi

Chiaki Dono

Hiromichi Fujisawa

Masaaki Fujinawa

Yasuo Kurosu

Masanori Isoda

Shinji Bessho

Masayuki Hira

Takeshi Sakata

Takayuki Kawahara

Masakazu Aoki

Hiroshi Watanabe

Satoru Yamada

Isamu Asano

Yasushi Takahashi

Kazuyoshi Oshima

Shinichiro Kimura

Hitoshi Tanaka

Jun Etoh

Norikatsu Takaura

Koji Arai

Ryo Nagai

Tetsuro Matsumoto

Hiroshi Kawamoto

Takashi Yunogami

Yuzuru Ohji

Hideharu Yahata

Hiroshi Otori

Yuji Yokoyama

Yoshihiro Shima

Toru Kosaka

Masashi Koga

Satoshi Ito

Katsuo Komatsuzaki

Hitoshi Fujita

Makoto Saeki

Masayoshi Hirasawa

Kanehide Kenmizaki

Hiroshi Meguro

Hiroshi Sakou

Eiichi Hadano

Shigeki Ueda

Tatsuya Sakamoto

Satomi Horita

Hiroshi Okamoto

Kiyomichi Kurino

Chisa Makimura

Akimitsu Mimura

Noriaki Kubota

Minoru Ebihara

Masayoshi Nomura

A logic circuit includes a setting circuit which holds and outputs setting information, a first flip-flop which holds data written to the setting circuit and outputs it in synchronization with an inputted clock, a second flip-flop which holds a write address for selecting the setting circuit and outputs it in synchronization with the inputted clock, and a third flip-flop which holds write enable which allows writing to the setting circuit and outputs it in synchronization with the inputted clock, wherein the setting circuit includes a fourth flip-flop which holds the setting information in synchronization with a given timing signal, and a fifth flip-flop which holds the output of the third flip-flop and outputs a write clock to the fourth flip-flop as the timing signal in synchronization with the inputted clock.

Logic circuit and method for controlling a setting circuit

A three dimensional integrated circuit includes a master circuit, a slave circuit, and a through-silicon via (TSV). The master circuit is configured to receive and process an input data, a data strobe signal (DQS) and an input command to output a writing data signal to a master die. The through-silicon via (TSV) is electrically coupled between the master circuit and the slave circuit. The master circuit is configured to transfer the writing data signal to a slave die through the TSV. Furthermore, a method for controlling a three dimensional integrated circuit is disclosed herein.

Three dimensional integrated circuit and method for controlling the same

A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups.

Signal transmission/reception circuit

An optical receiving apparatus with frame synchronization technology which makes it easy to activate a frame synchronization established state even if bit errors are produced over a transmission link. The apparatus includes: an optoelectrical converting circuit; a pre-stage synchronizing word detecting circuit; a decoder; a post-stage frame synchronization detecting circuit; and a receiver frame synchronization display output circuit.

Optical transceiving system with frame synchronization and optical receiving apparatus

If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted.

Data transmission

While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal.

Frame pulse signal latch circuit and phase adjustment method

An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.

Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit

A frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially is presented. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits.

Communication system

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed

In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Semiconductor integrated circuit

A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLK'; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit.

Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors

Growing community of inventors

Hamura, Japan

Tsugio Takahashi