Seiko Epson Corporation

Tsugio Nakamura

Tatsuya Shimoda

Kazuhiko Amano

Hiroshi Kasahara

An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (-to-x), each computing at an arithmetic precision 2bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x&#x2267;2/2is satisfied. When an arithmetic precision of 2bits (where n1&#x2266;n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1&#x2267;2/2(where x1 is a natural number and is variable) is satisfied. This makes it possible to easily implement an information processing system for performing computations to any desired precision in a hardware manner, and also makes it possible to support a simple hardware-based method of expanding the arithmetic precision.

Information processing system, encryption/decryption system, system LSI, and electronic equipment

An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units ( - to -x), each computing at an arithmetic precision 2 bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2 bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x&gE;2 /2 is satisfied. When an arithmetic precision of 2 bits (where n &lE;n, and n is variable) is necessary during computational processing, x numbers of the arithmetic units are cascaded in a manner such that the inequality x &gE;2 /2 (where x is a natural number and is variable) is satisfied. This makes it possible to easily implement an information processing system for performing computations to any desired precision in a hardware manner, and also makes it possible to support a simple hardware-based method of expanding the arithmetic precision.

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Nagareyama, Japan

Tsugio Nakamura